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SOCRATES - A HIGHLY EFFICIENT AUTOMATIC TEST PATTERN GENERATION SYSTEM

IEEE TRANSACTIONS ON computer-aided design OF INTEGRATED CIRCUITS AND SYSTEMS 1988年第1期7卷 126-137页

作者： SCHULZ, MH TRISCHLER, E SARFERT, TM Institute of Computer Aided Design Department of Electrical Engineering Technical University Munich Munich Germany Department E STE 4 CAD/CAT Siemens AG Munich Germany

An automatic test pattern generation system, SOCRATES, is presented. SOCRATES includes several novel concepts and techniques that significantly improve and accelerate the automatic test pattern generation process for combinational and scan-based circuits. Based on the FAN algorithm, improved implication, sensitization, and multiple backtrace procedures are described. The application of these techniques leads to a considerable reduction of the number of backtrackings and an earlier recognition of conflicts and redundancies. Several experiments using a set of combinational benchmark circuits demonstrate the efficiency of SOCRATES and its cost-effectiveness, even in a workstation environment.< >

关键词： Automatic test pattern generation Circuit testing Test pattern generators Circuit faults Automatic testing Costs Benchmark testing Workstations Very large scale integration design for testability

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GORDIAN: a new global optimization/rectangle dissection method for cell placement

GORDIAN: a new global optimization/rectangle dissection meth...

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IEEE International Conference on computer-aided design

作者： J.M. Kleinhans G. Sigl F.M. Johannes Institute of Computer-Aided Design Department of Electrical Engineering Technical University Munich Munich Germany

A placement method for cell-based layout styles composed of alternating and interacting global optimization and partitioning phases is presented. In contrast to other methods using the divide-and-conquer paradigm, it maintains the simultaneous treatment of all cells during optimization over all levels of partitioning. In the global optimization phases, constrained quadratic optimization problems with unique global minima are solved. Their solutions induce the assignment of cells to regions during the partitioning phases. For general-cell circuits, a highly efficient exhaustive slicing procedure is applied to small subsets of cells. The designer may choose a configuration from a menu to meet his requirements on chip area, chip aspect ratio and wire length. Placements with high area utilization are obtained within short computation times. The method has been applied to general-cell and standard-cell circuits with up to 3000 cells and nets.< >

关键词： Optimization methods Constraint optimization Circuits Partitioning algorithms Iterative algorithms design optimization design automation Wire Very large scale integration

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Advanced automatic test pattern generation and redundancy identification techniques

Advanced automatic test pattern generation and redundancy id...

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International Symposium on Fault-Tolerant Computing (FTCS)

作者： M.H. Schulz E. Auth Institute of Computer Aided Design Department of Electrical Engineering Technical University Munich Munich Germany

Based on the sophisticated strategies used in the automatic test pattern generation system SOCRATES, the authors present several concepts aiming at a further improvement and acceleration of the deterministic test pattern generation and redundancy identification process. In particular, they describe an improved implication procedure and an improved unique sensitization procedure. Both procedures significantly advance the deterministic test pattern generation and redundancy identification especially for those faults, for which it is difficult to generate a test pattern or to prove them to be redundant, respectively. As a result of the application of the proposed techniques, SOCRATES is capable of successfully generating a test pattern for all testable faults in a set of combinational benchmark circuits, and of identifying all redundant faults with less than 10 backtrackings.< >

关键词： Automatic test pattern generation Circuit faults Circuit testing Test pattern generators Redundancy Fault diagnosis Combinational circuits Life estimation Benchmark testing Very large scale integration

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ACCELERATED FAULT SIMULATION AND FAULT GRADING IN COMBINATIONAL-CIRCUITS

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IEEE TRANSACTIONS ON computer-aided design OF INTEGRATED CIRCUITS AND SYSTEMS 1987年第5期6卷 704-712页

作者： ANTREICH, KJ SCHULZ, MH Institute of Computer Aided Design Department of Electrical Engineering Technical University Munich Munich Germany

The principles of fault simulation and fault grading are introduced by a general description of the problem. Based upon the well-known concept of restricting fault simulation to the fanout stems and of combining it with a backward traversal inside the fanout-free regions of the circuit, proposals are presented to further accelerate fault simulation and fault grading. These proposals aim at parallel processing of patterns at all stages of the calculation procedure, at reducing the number of fanout stems for which a fault simulation has to be carried out, and at taking advantage of structural characteristics of the circuit. An experiment with a set of benchmark circuits demonstrates the efficiency of the proposed approaches.

关键词： Circuit faults Acceleration Circuit simulation Combinational circuits Circuit testing Proposals Costs Computational modeling Very large scale integration Sequential analysis

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An entrepreneur's guide to financing the high technology company

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Optics News 1987年第10期13卷 6-9页

作者： Thomas H. Bruggere THOMAS H. BRUGGERE is president and chief executive officer of Mentor Graphics Corporation Beaverton Oregon. He founded the company in 1981 to produce products for the electronics portion of the computer-aided design industry.

No abstract available.

关键词： Crosstalk Energy Reflection

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GENERAL ARRANGEMENT design computer-SYSTEM AND METHODOLOGY .1. GENERAL ARRANGEMENT design SYSTEM

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NAVAL ENGINEERS JOURNAL 1987年第3期99卷 261-273页

作者： CARLSON, CM FIREMAN, H Craig M. Carlson:is a general engineer in the Computer Aided Engineering Division (SEA-507). He received his B.S. degree in naval architecture from the University of Michigan in 1970. In 1972 he was selected for the NAVSEC Hull Division's Long Term Training Program at the University of Michigan and received his M. S. E. degree in naval architecture in 1973. Additionally he has done graduate work in computer science at The Johns Hopkins University. Mr. Carlson began his career with the Naval Ship Engineering Center in 1970 where he worked in the Ship Arrangements Branch. While in ship arrangements he was task leader for the PGG PCG PHM and MCM ship designs. In addition he was project engineer for shipboard stowage ship space classification system and ship standard nomenclature. He was technical manager of the CASDAC arrangement subsystem and the CASDAC hull design system. In 1982 he joined what is now the Computer Aided Engineering Division. Currently he is the manager for the computer supported design version XX system. Besides ASNE which he joined in 1972 he is a member of SNA ME and the U.S. Naval Institute. Howard Fireman:is a naval architect in the Ship Arrangements Design Division (SEA-55W1). He received his B. S. E. degree in naval architecture from the University of Michigan in 1979. In 1983 he was selected for NavSea's Long Term Training Program at the University of Michigan and received his M. S. E. degree in naval architecture with a specialization in ship production and computer aided ship design in 1985. Mr. Fireman began his career with the Naval Ship Engineering Center in 1977 as an engineering cooperative student. Since graduating from the NavSea EIT program he has worked in the Ship Arrangements Design Division. He was task leader for the AOE-6 AE-36 T-AH ARS-SO and SWATH T-AGOS ship designs. He is technical manager of the CSD General Arrangement Design System and is currently the Hull Group CSD coordinator. Besides ASNE which he joined in 1979 he is a member of SNA ME ASE a

The ever increasing complexity of ships coupled with cost, schedule, and resource constraints require innovative methods by the Naval Sea Systems Command's ship design community to meet this challenge. This paper describes the effort by the NavSea Ship Arrangement design Division to dramatically improve its ship design capability by the use of a system of computer-based design tools called the General Arrangement design System. The General Arrangement design System (GADS) is based on the engineering requirements of the ship arrangement design process. GADS is currently being used as a production engineering tool. This paper is organized into two parts. Part I describes the General Arrangement design System, and Part II describes the general arrangement design methodology.

关键词： NAVAL ARCHITECTURE

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On the relative placement and the transportation problem for standard-cell layout

On the relative placement and the transportation problem for...

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23rd ACM/IEEE design Automation Conference, DAC 1986

作者： Just, Knut M. Kleinhans, Jürgen M. Johannes, Frank M. Institute of Computer-Aided Design Department of Electrical Engineering Technical University of Munich Germany

ISBN: (纸本)0818607025

A new two-phased method for the simultaneous placement of modules for standard-cell layout is presented. In phase one, a relative placement is calculated by application of an iterative solution method taking advantage of net-list sparsity. A fast algorithm is derived from a new formulation of the problem. In addition, signal weights and pin coordinates are considered. In phase two, different-sized modules are assigned to physical locations by solving a transportation problem. © 1986 IEEE.

关键词： computer aided design

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On the Relative Placement and the Transportation Problem for Standard-Cell Layout

On the Relative Placement and the Transportation Problem for...

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design Automation Conference

作者： K.M. Just J.M. Kleinhans F.M. Johannes Institute of Computer-Aided Design Department of Electrical Engineering Technical University Munich Germany Institute of Computer-Aided Design Department of Electrical Engineering Technical University of Munich Spain

关键词： Transportation Wire Topology Circuits design automation Iterative methods Iterative algorithms Very large scale integration Partitioning algorithms Government

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On the relative placement and the transportation problem for standard-cell layout 86

On the relative placement and the transportation problem for...

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Proceedings of the 23rd ACM/IEEE design Automation Conference

作者： Knut M. Just Jürgen M. Kleinhans Frank M. Johannes Institute of Computer-Aided Design Department of Electrical Engineering Technical University of Munich

ISBN: (纸本)9780818607028

A new two-phased method for the simultaneous placement of modules for standard-cell layout is presented. In phase one, a relative placement is calculated by application of an iterative solution method taking advantage of net-list scarcity. A fast algorithm is derived from a new formulation of the problem. In addition, signal weights and pin coordinates are considered. In phase two, different-sized modules are assigned to physical locations by solving a transportation problem.

关键词：

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DEVELOPMENTS IN SWATH TECHNOLOGY

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NAVAL ENGINEERS JOURNAL 1986年第3期98卷 171-188页

作者： GUPTA, SK SCHMIDT, TW Sudhir “S.K.” Guptais currently manager technical programs at Lockheed Shipbuilding Company Seattle Washington. He graduated from the Marine Engineering College India in 1972 and spent eight years as a marine engineer on commercial ships including service as a licensed chief engineer. In 1981 he received his BSE degree in naval architecture and marine engineering from the University of Michigan. Before joining LSC Mr. Gupta worked with Designers and Planners Inc. His current responsibilities include management of SWA TH design and development efforts. Other experience has been in the fields of computer aided design and early-stage ship design. He received the Robert E. Gross Award for Technical Excellence as Engineer/Scientist of the Year from Lockheed Corporation in 1984 for his stability studies on LSD-41 class ships. Mr. Gupta has earlier presented technical papers on ship production and diesel engines. He is a member of SNAME ASNE RINA Institute of Marine Engineers and is registered as a chartered engineer in U.K. and in India. Terrence W. Schmidtgraduated from California State Polytechnic University in 1966 receiving his BS degree in aeronautical engineering. He received his MS degree in mechanical engineering from San Jose State University. Mr. Schmidt is currently a group leader at Lockheed Advanced Marine Systems Santa Clara previously known as the Ocean Systems Division of Lockheed Missile and Space Company. A key participant on all SWATH projects his work led to him being awarded the Robert E. Gross A ward for Technical Excellence as Engineer/Scientist of the Year in 198S. His responsibilities include hydrodynamic design development and analysis of SWATH ships. He has performed experimental and analytical studies on a variety of advanced marine vehicles. From 1966 to 1973 Mr. Schmidt worked at ARO Inc. as a project engineer responsible for planning conducting and documenting wind tunnel test programs. Models included missiles aircraft and marine vehicles.

It has been over two decades since the start of SWATH technology development began in earnest. SWATH is no longer an “emerging” technology. SWATH ships are now state of the art and the technology has come of age. With the construction of the 3500 ton Kaiyo in Japan, SWATH vessels have moved from prototypes and demonstrators to modern, high performance working vessels. A number of new design techniques have been developed which enhance the seakeeping and maneuvering capability of these ships. Other concepts currently being developed include producibility improvements, structural design manuals, cost and weight estimation standards, and performance predictions based on scale models. A synthesis computer program has been developed for conceptual design based on existing SWATH ships and designs.

关键词： SHIPS

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