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MESSI: Task Mapping and Scheduling Strategy for FPGA-based Heterogeneous Real-Time systems

ACM Transactions on Design Automation of Electronic systems 2025年第3期30卷 1-29页

作者： Ahmadi-Pour, Sallar Saha, Sangeet Mcdonald-Maier, Klaus Drechsler, Rolf Institute of Computer Science University of Bremen Faculty 3 Mathematics and Computer Science Bremen Bremen Germany Robotics and Embedded Systems Research Group University of Essex School of Computer Science and Electronic Engineering Colchester United Kingdom Cyber-Physical Systems DFKI Rheinland-Pfalz Kaiserslautern Germany

Continuous demands for improved performance within constrained resource budgets are driving a move from homogeneous to heterogeneous processing platforms for the implementation of today's Real-Time (RT) embedded systems. The applications executing on such systems are typically represented as a Precedence Task Graph (PTG), where a node represents a task or algorithm for one functionality and edges represent the complex interactions between multiple functionalities. Due to RT constraints, the task graph needs to be executed within a specified deadline. Although some existing studies have looked into solving this challenge, comprehensive studies that combine the theoretical features of RT task-graph mapping and scheduling with practical runtime architectural characteristics have mostly been ignored to date. Hence, in this article, we consider the challenge of scheduling an RT application modeled as a single PTG, with the objective of minimizing the overall execution time under Hardware (HW) resource and deadline constraints for heterogeneous Central Processing Unit (CPU) + Field Programmable Gate Array (FPGA) architectures. First, we introduce an optimal solution using Integer Linear Programming (ILP). However, this ILP-based optimal solution suffers from computational complexity and does not scale well even for moderately large problem sizes. Hence, we additionally propose heuristic algorithms for task mapping and scheduling. The efficiency of the proposed scheme, named MESSI, has been evaluated through experiments using PTG on a practical CPU+FPGA system regarding current technology restrictions. Our experiments demonstrate that performance gains of 55.6% and area usage reductions of 46.3% are possible compared to full Software (SW) and HW execution, respectively. © 2025 Copyright held by the owner/author(s). Publication rights licensed to ACM.

关键词： Integer programming

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FPGARLab: Leveraging FPGA Design and Verification Using Intelligent Cyber Physical System Based Collaborative Remote Laboratory 6

FPGARLab: Leveraging FPGA Design and Verification Using Inte...

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6th International Congress on Human-computer Interaction, Optimization and Robotic Applications, HORA 2024

作者： Al Amin, Rashed Wiese, Veit Rahman, Mohammad Musfiqur Jacobs, Sven Jaschke, Steffen Obermaisser, Roman Institute for Embedded Systems University of Siegen Siegen Germany Computer Science Education University of Siegen Siegen Germany

ISBN: (纸本)9798350394634

The Field-Programmable Gate Arrays (FPGAs) computing architecture allows users to program and reconfigure hardware, providing flexibility and adaptability. FPGAs have garnered considerable attention in both academic research and industrial contexts due to their potential applications. Teaching hardware design, requiring direct access to specific hardware platform for conclusive testing, faces challenges with FPGAs, which are not easily shared among multiple users. The rising use of remote laboratory systems has addressed this constraint, allowing access to various equipment and devices from different geographic locations, has witnessed an upsurge in engineering education and industrial research. The traditional laboratory approach has transformed with the integration of computers, electronic devices, and the internet, giving rise to a novel paradigm in laboratory practice known as the remote laboratory system. This system allows users to access lab equipment at their convenience, fostering self-paced learning. This paper demonstrates an intelligent cyber physical system based platform for remote FPGA kit access, facilitating collaborative task-solving through a web interface. Tailored for FPGAs, the system autonomously manages logic design, synthesis, and simulation. Acting as a gateway, it provides users fully control over FPGA development boards, including peripherals with real-time feedback via video streaming and live chat. This proposed intelligent cyber-physical system also possesses the capability to oversee multiple and diverse FPGA development boards through smart light control and power-saving mode, thereby augmenting the system's overall efficiency. This distinctive design offers the advantage of conducting student laboratory exercises or industrial training where FPGA hardware must be accessed by numerous users simultaneously. © 2024 IEEE.

关键词： Field programmable gate arrays (FPGA)

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RUL Estimation for Power Electronic Devices Using RNNs

RUL Estimation for Power Electronic Devices Using RNNs

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2024 Prognostics and System Health Management Conference, PHM 2024

作者： Cai, Congrui Lu, Zhonghai School of Electrical Engineering and Computer Science KTH Royal Institute of Technology Embedded Systems Master Program Sweden School of Electrical Engineering and Computer Science Department of Electrical Engineering KTH Royal Institute of Technology Sweden

ISBN: (纸本)9798350360585

Recurrent Neural Networks (RNNs) are commonly used in data-driven approaches to estimate the Remaining Useful Lifetime (RUL) of power electronic devices. RNNs are preferred because their intrinsic feedback mechanisms are better suited to model time-series data. However, the impact of RNN complexity on estimation accuracy is rarely discussed in the literature. This issue is important because choosing a lower-complexity model that delivers the same or similar performance as a higher-complexity model can increase implementation efficiency. In the paper, we use three RNN models, namely, the vanilla version, LSTM (Long Short Term Memory) and GRU (Gated Recurrent Unit) to conduct RUL estimation for power electronic devices. We use two accelerated aging datasets, one dataset targeting the package failure of MOSFETs, and the other dataset targeting package failure of power diodes. Our study shows that a lower-complexity RNN does not necessarily deliver a lower performance. Similarly, a higher-complexity model does not assure a higher performance. As such, our work highlights the importance of selecting a proper neural network for RUL estimation not biased towards complex models. This is especially useful and important for implementing such RUL estimation techniques in embedded resource-constrained and speed-limited computins platforms. © 2024 IEEE.

关键词： Long short-term memory

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Challenges and Initial Measurements on Communication and Localization for Mountain Bike Safety Applications 20

Challenges and Initial Measurements on Communication and Loc...

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20th Wireless On-Demand Network systems and Services Conference, WONS 2025

作者： Zucchelli, Michele Marx, Marcus Hörmann, Max Kargl, Frank Segata, Michele University of Trento Department of Information Engineering and Computer Science Italy Ulm University Institute of Distributed Systems Germany

ISBN: (纸本)9783903176713

As of today, research in vulnerable road users (VRUs) applications is mainly focused on safety in urban road scenarios. There is little to be found in the literature with respect to VRUs in mountain areas, where mountain biking and hiking also present risks of collision. Here, it is not yet clear whether existing localization and communication technologies would provide sufficient performance in such harsh environments. In this work, we start answering this question by presenting the results of a measurement campaign which took place in a mountain area in Northern Italy during Summer 2024. With respect to localization, we show that global navigation satellite system (GNSS)-based localization alone often provides unreliable results due to vegetation and terrain. Trilateration with Bluetooth Low Energy (BLE) and beacons mounted at fixed positions performs well in some circumstances and can be used to enhance GNSS, however, we also observed many unclear effects that require further investigations. Concerning communication, the results indicate that both direct short range communications (DSRC) and cellular V2X (C-V2X) works fairly well in most cases, but terrain characteristics might induce packet losses or low signal quality, whereas instabilities in GNSS fixes might also cause C-V2X outages. © 2025 IFIP.

关键词： Global positioning system

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Towards a Unified Flow Description Language for CPPSs: An Example with Material Flows 29

Towards a Unified Flow Description Language for CPPSs: An Ex...

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29th IEEE International Conference on Emerging Technologies and Factory Automation, ETFA 2024

作者： Gödeke, Jana Hörstrup, Maximilian Detzner, Peter Fraunhofer Institute for Material Flow and Logistics Department for Ai and Autonomous Systems Dortmund Germany Ruhr University Bochum Faculty of Computer Science Distributed and Networked Systems Group Bochum Germany

ISBN: (纸本)9798350361230

This paper presents a unified approach for repre-senting multiple domains alongside production in cyber-physical production systems (CPPSs) through domain-specific languages (DSLs). The approach is illustrated using material flows (MFs) as an example. The paper identifies requirements for DSLs in CPPSs and MFs, including concurrency, synchronization, constraints, and heterogeneity support. Subsequently, a plugin system is in-troduced for the existing Production Flow Description Language (PFDL), which allows users to incorporate additional domain-specific functionality in the form of plugins. To demonstrate this approach, we present the MF plugin, resulting in the combined PFDLMF. This showcases the reusability of such an approach and the easy integration of new CPPS domains. We envision the convergence of the PFDL with plugins towards a unified flow description language for CPPSs. A practical CPPS use-case demonstrates the expressiveness of the PFDLMF in modeling and executing complex MFs in an agent-based architecture. © 2024 IEEE.

关键词： Reusability

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Hybrid PTX Analysis for GPU accelerated CNN inferencing aiding computer Architecture Design

Hybrid PTX Analysis for GPU accelerated CNN inferencing aidi...

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2023 Forum on Specification and Design Languages, FDL 2023

作者： Metz, Christopher A. Plump, Christina Berger, Bernhard J. Drechsler, Rolf Cyber-Physical Systems DFKI GmbH Bremen Germany Institute of Computer Science University of Bremen Bremen Germany Institute of Embedded Systems Hamburg University of Technology Hamburg Germany

ISBN: (纸本)9798350307375

General-Purpose Computation on Graphics Processing Units (GPGPUs) are becoming crucial in accelerating computing capacity. Due to the massive parallelism capabilities of GPUs, they can achieve impressive speedups of up to 32 times compared to common CPUs. However, writing highly parallel code and utilizing a GPU is challenging for programmers. Developers are facing new challenges since GPUs handle threads and parallelism differently from CPUs. Academia and industry proposed several profilers to support developers in terms of code optimization. These profilers often require an actual device (e.g., GPU) and take a long time for the profiling process. We propose HyPA, a hybrid Parallel Thread Execution (PTX) Analyzer that inspects PTX code statically and dynamically. HyPA implements a partly functional emulator that executes instructions that rely on runtime dependencies to count the number of executed PTX instructions and divergent branches. HyPa executes compiled kernels-the programs that run on GPUs-generated by the CUDA compiler and supports the full PTX 7.7 specification. Our functional emulator allows significantly faster analysis of PTX code compared to standard profilers. In our evaluation, we quantify this increase in performance through benchmark runs. HyPA achieved speedups of up to 536% compared to the nvprof profiler. Moreover, our approach can gather performance metrics beyond static analysis (e.g., branch efficiency) by a faster execution time than by profiling the application on an actual device. Finally, we provide an open-source implementation of HyPA to help developers and system designers in further research and development. copy;2023 IEEE. © 2023 IEEE computer Society. All rights reserved.

关键词： Graphics processing unit

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Database Deadlock Diagnosis for Large-Scale ORM-Based Web Applications 39

Database Deadlock Diagnosis for Large-Scale ORM-Based Web Ap...

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39th IEEE International Conference on Data Engineering, ICDE 2023

作者： Dong, Zhiyuan Wang, Zhaoguo Yi, Chuanwei Xu, Xian Zhang, Jinyuan Li, Jinyang Chen, Haibo Shanghai Jiao Tong University Institute of Parallel and Distributed Systems China New York University Department of Computer Science United States

ISBN: (纸本)9798350322279

Today, most database-backed web applications depend on the database to handle deadlocks. At runtime, the database monitors the progress of transaction execution to detect deadlocks and abort affected transactions. However, this common detect-and-recover strategy is costly to performance as aborted transactions waste CPU *** avoid deadlock-induced performance degradation, developers aim to reorganize the application code to remove deadlocks. Unfortunately, doing so is difficult for web applications. Not only do their implementations include hundreds of thousands of LoCs, but they also use third-party object-relational mapping (ORM) frameworks which hide database access details. Consequently, it is hard for developers to accurately diagnose *** propose WeSEER, a deadlock diagnosis tool for web applications. To overcome the opacity of ORMs, WeSEER performs concolic execution on unit tests to extract a web application's transactions as a sequence of template statements with symbolic inputs as well as path conditions that enable the sequence. WeSEER then analyzes the extracted transactions based on fine-grained lock modeling to identify potential deadlocks and report the code locations that cause them. We implement WeSEER for Java-based (OpenJDK) web applications, and use it to analyze two popular open-source e-commerce applications, Broadleaf and Shopizer. WeSEER has successfully identified 18 potential deadlocks in Broadleaf and Shopizer. Eliminating these identified deadlocks can result in up to 39.5× and 4.5× throughput improvement for Broadleaf and Shopizer, respectively. © 2023 IEEE.

关键词： Database systems

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Scalable and Low-Cost Remote Lab Platforms: Teaching Industrial Robotics Using Open-Source Tools and Understanding Its Social Implications 16th

Scalable and Low-Cost Remote Lab Platforms: Teaching Indust...

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16th International Conference on Social Robotics, ICSR + AI 2024

作者： Kumar, Amit Jose, Jaison Jain, Archit Kulkarni, Siddharth Arya, Kavi Centre for Systems and Control Indian Institute of Technology Bombay Mumbai India Embedded Real-Time Systems / e-Yantra Lab Indian Institute of Technology Bombay Mumbai India Computer Science and Engineering Department Indian Institute of Technology Bombay Mumbai India

ISBN: (纸本)9789819635214

With recent advancements in industrial robots, educating students in new technologies and preparing them for the future is imperative. However, access to industrial robots for teaching poses challenges, such as the high cost of acquiring these robots, the safety of the operator and the robot, and complicated training material. This paper proposes two low-cost platforms built using open-source tools like Robot Operating System (ROS) and its latest version ROS 2 to help students learn and test algorithms on remotely connected industrial robots. Universal Robotics (UR5) arm and a custom mobile rover were deployed in different life-size testbeds, a greenhouse, and a warehouse to create an Autonomous Agricultural Harvester System (AAHS) and an Autonomous Warehouse Management System (AWMS). These platforms were deployed for a period of 7 months and were tested for their efficacy with 1,433 and 1,312 students, respectively. The hardware used in AAHS and AWMS was controlled remotely for 160 and 355 hours, respectively, by students over a period of 3 months. © The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2025.

关键词： Costs

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Fine-Grained Re-Execution for Efficient Batched Commit of distributed Transactions 49th

Fine-Grained Re-Execution for Efficient Batched Commit of Di...

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49th International Conference on Very Large Data Bases, VLDB 2023

作者： Dong, Zhiyuan Wang, Zhaoguo Zhang, Xiaodong Xu, Xian Zhao, Changgeng Chen, Haibo Panda, Aurojit Li, Jinyang Institute of Parallel and Distributed Systems Shanghai Jiao Tong University China Department of Computer Science New York University United States

distributed transaction systems incur extensive cross-node communication to execute and commit serializable OLTP transactions. As a result, their performance greatly suffers. Caching data at nodes that execute transactions can cut down remote reads. Batching transactions for validation and persistence can amortize the communication cost during committing. However, caching and batching can significantly increase the likelihood of conflicts, causing expensive aborts. In this paper, we develop Hackwrench to address the challenge of caching and batching. Instead of aborting conflicted transactions, Hackwrench tries to repair them using fine-grained re-execution by tracking the dependencies of operations among a batch of transactions. Tracked dependencies allowHackwrench to selectively invalidate and re-execute only those operations necessary to "fix" the conflict, which is cheaper than aborting and executing an entire batch of transactions. Evaluations using TPC-C and other micro-benchmarks show that Hackwrench can outperform existing commercial and research systems including FoundationDB, Calvin,COCO, and Sundial under comparable settings. © 2023, VLDB Endowment. All rights reserved.

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Two-Stage Hybrid Edge Caching Framework for 360° VR Video

Two-Stage Hybrid Edge Caching Framework for 360° VR Video

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IEEE International Symposium on World of Wireless Mobile and Multimedia Networks (WoWMoM)

作者： Chuyang Gao Torsten Braun Communication and Distributed Systems Institute of Computer Science University of Bern Switzerland

ISBN: (数字)9798331538323

ISBN: (纸本)9798331538330

The advent of virtual reality and immersive communication technologies is effecting a transformation in user experiences, enabling high-quality, low-latency interactions. In order to meet these requirements, edge caching, in particular for the transmission of virtual reality content, has become an efficient strategy for the mitigation of transmission latency and the decrease of backhaul traffic loads. This paper provides an introduction to a two-stage hybrid caching framework developed to manage the typical obstacles related to the caching of 360° video. The proposed framework comprises two stages: a learning stage, which employs a Deep Q-Network to predict cache replacement actions, and a solving stage, which utilizes Integer Linear Programming to refine and optimize caching decisions. Furthermore, an L2 edge cache architecture is designed with the goal of enhancing cache utilization and further alleviating backhaul traffic. Performance evaluations illustrate that the proposed framework significantly enhances the cache hit ratio and reduces latency and backhaul usage compared to other methods.

关键词： Performance evaluation Wireless communication Prevention and mitigation Neural networks Virtual reality Telecommunication traffic Integer linear programming Low latency communication Optimization Backhaul networks

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