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ADAPT: An adaptive manycore methodology for software pipelined applications

ADAPT: An adaptive manycore methodology for software pipelin...

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Asia and South Pacific Design Automation Conference

作者： Xi Zhang Haris Javaid Muhammad Shafique Jude Angelo Ambrose Jörg Henkel Sri Parameswaran School of Computer Science and Engineering University of New South Wales Sydney Australia Google Inc. Chair for Embedded Systems Karlsruhe Institute of Technology Karlsruhe Germany

ISBN: (纸本)9781479977932

Future on-chip manycore systems are expected to have hundreds of cores, and to be used for a number of applications to amortize their fabrication costs. In this paper, we examine how software pipelines, which are useful for streaming/multimedia applications, can be efficiently executed on a manycore system with shared memory. The goal is to balance the stages of the pipeline under workload and resource variations. This paper presents ADAPT, a method to quickly detect bottleneck stages and add cores (workers) to those bottleneck stages at run-time. Further, if there are no idle workers, then a shuffling of workers across stages is performed to improve/maintain throughput. ADAPT is implemented in a 48-core system which is built using a commercial core and tool suite. For a variety of applications, ADAPT takes less than 2 μs for one run-time adaptation, and achieves up to 2.1× the throughput of a state-of-the-art method (which is modified and implemented in the same system for a fair comparison). These results illustrate the applicability of ADAPT for fine-grained run-time management of manycore systems to achieve high throughput for software pipelines.

关键词： Pipelines Delays Software Throughput Pipeline processing Steady-state Dynamic scheduling

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E-pipeline: Elastic hardware/software pipelines on a many-core fabric 15

E-pipeline: Elastic hardware/software pipelines on a many-co...

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Design, Automation and Test in Europe Conference and Exhibition

作者： Xi Zhang Haris Javaid Muhammad Shafique Jorgen Peddersen Jörg Henkel Sri Parameswaran School of Computer Science and Engineering University of New South Wales Sydney Australia Google Inc. Chair for Embedded Systems Karlsruhe Institute of Technology Karlsruhe Germany

ISBN: (纸本)9783981537048

On-chip many-core systems are expected to be in common use in the future. A set of homogeneous processors in a many-core system can be used to implement multiple pipelines which execute simultaneously. Pipelines of processors use varying numbers of cores when their workloads vary at run time. In this paper, we show how such a system executing multiple pipelines with varying workloads can be implemented. We further show how the system can switch cores within a pipeline (intra-elasticity) and between pipelines (inter-elasticity). The method is named E-pipeline, and is implemented and evaluated in a commercial tool suite. Compared to reference design methods with clock gating, E-pipeline achieves the same power savings, maintains the throughput to meet throughput constraints and reduces core usage by an average of 37.7%. The adaptation overhead for switching cores is approximately 2μs.

关键词： Pipelines Throughput Software Cloning Benchmark testing Clocks Hardware

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Reconfigurable communication fabric for efficient implementation of neural networks

Reconfigurable communication fabric for efficient implementa...

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International Workshop on Reconfigurable Communication-Centric systems-on-Chip (ReCoSoC)

作者： Arash Firuzan Mehdi Modarressi Masoud Daneshtalab Department of Computer Engineering Pooyesh Institute of Higher Education Iran School of Computer Science Institute for Researches in Fundamental Sciences Tehran Iran School of Electrical and Computer Engineering University of Tehran Tehran Iran Department of Electronic and Embedded Systems Royal Institute of Technology Sweden

Handling heavy multicast-based inter-neuron communication is the most challenging issue in parallel implementation of neural networks. To address this problem, a reconfigurable Network-on-Chip (NoC) architecture for neural networks is presented in this paper. The NoC consists of a number of node clusters with a fix topology connected by a reconfigurable inter-cluster communication fabric that efficiently handles multicast communication. The evaluation results show that the proposed architecture can better manage the multicast-based traffic of neural networks than the mesh-based topologies proposed in prior work. It offers up to 60% and 22% lower average message latency compared to a baseline and a state-of-the-art NoC for neural networks, respectively, which directly translates to faster neural processing.

关键词： Neural networks Neurons Topology Network topology computer architecture Program processors Clustering algorithms

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SuperNet: Multimode interconnect architecture for manycore chips

SuperNet: Multimode interconnect architecture for manycore c...

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Design Automation Conference

作者： Haseeb Bokhari Haris Javaid Muhammad Shafique Jörg Henkel Sri Parameswaran School of Computer Science and Engineering University of New South Wales Sydney Australia Google Inc. USA Chair for Embedded Systems Karlsruhe Institute of Technology Karlsruhe Germany

Designers of the on-chip interconnect for manycore chips are faced with the dilemma of meeting performance, power and reliability requirements for different operational scenarios. In this paper, we propose a multimode on-chip interconnect called SuperNet. This interconnect can be configured to run in three different modes: energy efficient mode; performance mode; and, reliability mode. Our proposed interconnect is based on two parallel multi-vt optimized packet switched network-on-chip (NoC) meshes. We describe the circuit design techniques and architectural modifications required to realize such a multimode interconnect. Our evaluation with diverse set of applications show that the energy efficient mode can save on average 40% NoC power, whereas the performance mode can improve the core IPC by up to 13% on selected high MPKI applications. The reliability mode provides protection against soft errors in the router's data path through byte oriented SECDED codes that can correct up to 8 bit errors and detect up to 16 bit errors in a 64 bit flit, whereas the router's control path is protected through DMR lock step execution.

关键词： Frequency modulation Reliability computer architecture System-on-chip Switches Microprocessors

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Towards inter-vehicle communication strategies for platooning support 7

Towards inter-vehicle communication strategies for platoonin...

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2014 7th International Workshop on Communication Technologies for Vehicles, Nets4Cars-Fall 2014

作者： Segata, Michele Bloessl, Bastian Joerer, Stefan Sommer, Christoph Gerla, Mario Cigno, Renato Lo Dressler, Falko Computer and Communication Systems Institute of Computer Science University of Innsbruck Austria Systems and Networks Dept. of Information Engineering and Computer Science University of Trento Italy Distributed Embedded Systems Institute of Computer Science University of Paderborn Germany Dept. of Computer Science University of California Los AngelesCA United States

ISBN: (纸本)9781479952700

Platooning, the idea of cars autonomously following their leaders to form a road train, has huge potentials to improve traffic flow efficiency and, most importantly, road traffic safety. Wireless communication is a fundamental building block - it is needed to manage and to maintain the platoons. To keep the system stable, strict constraints in terms of update frequency and reliability must be met. We developed communication strategies by explicitly taking into account the requirements of the controller, exploiting synchronized communication slots as well as transmit power adaptation. The proposed approaches are compared to two state of the art adaptive beaconing protocols that have been designed for generic message dissemination. Our simulation models have been parametrized and validated by means of real-world experiments. We clearly show how taking into account specific requirements can be extremely beneficial even in very crowded freeway scenarios. © 2014 IEEE.

关键词： Roads and streets

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Malleable NoC: Dark silicon inspired adaptable Network-on-Chip 15

Malleable NoC: Dark silicon inspired adaptable Network-on-Ch...

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Design, Automation and Test in Europe Conference and Exhibition

ISBN: (纸本)9783981537048

Network on Chip (NoC) has been envisioned as a scalable fabric for many core chips. However, NoCs can consume a considerable share of chip power. Moreover, diverse applications are executed in these multicore, where each application imposes a unique load on the NoC. To realise a NoC which is Energy and Delay efficient, we propose combining multiple VF optimized routers for each node (in traditional NoCs, we have only a single router per node) for efficient NoC for Dark Silicon chips. We present a generic NoC with routers designed for different VF levels, which are distributed across the chip. At runtime, depending on application profile, we combine these VF optimized routers to form constantly changing energy efficient NoC fabric. We call our architecture Malleable NoC. In this paper, we describe the architectural details of the proposed architecture and the runtime algorithms required to dynamically adapt the NoC resources. We show that for a variety of multi program benchmarks executing on Malleable NoC, Energy Delay product (EDP) can be reduced by up to 46% for widely differing workloads. We further show the effect on EDP savings for differing amounts of dark silicon area budget.

关键词： Switches Silicon Multicore processing System-on-chip Runtime Clocks

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Response Policies to Process Module Failure in Single-Arm Cluster Tools Subject to Wafer Residency Time Constraints

Response Policies to Process Module Failure in Single-Arm Cl...

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作者： Qiao, Yan Pan, Chun-Rong Wu, Nai-Qi Zhou, Mengchu Department of Industrial Engineering School of Electro-Mechanical Engineering Guangdong University of Technology Guangzhou510006 China School of Mechatronics and Electrical Engineering Jiangxi University of Science and Technology Ganzhou341000 China Institute of Systems Engineering Macau University of Science and Technology Taipa China Key Laboratory of Embedded System and Service Computing Ministry of Education Tongji University Shanghai201804 China Department of Electrical and Computer Engineering New Jersey Institute of Technology NewarkNJ07102-1982 United States

In semiconductor manufacturing, wafer residency time constraints make the scheduling problem of cluster tools complicated. A process module (PM) in cluster tools is prone to failure. It is crucial to deal with any such failure in a proper and timely manner. If there are feasible periodic schedules in operating a cluster tool before and after a PM failure, it is desired to make it operate continuously when such a failure occurs. However, due to wafer residency time constraints, it is highly challenging to control a tool such that it can be correctly transferred from a feasible schedule before failure to another after it. To solve this problem, a Petri net model is developed to describe the dynamic behavior of a single-arm cluster tool and failure response policies are proposed. The proposed policies are formulated via simple control laws for their easy implementation. Examples are given to show them. © 2015 IEEE.

关键词： Scheduling

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Enforcing entailment constraints in offline editing scenarios for real-time collaborative web documents 14

Enforcing entailment constraints in offline editing scenario...

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29th Annual ACM Symposium on Applied Computing, SAC 2014

作者： Gaubatz, Patrick Hummer, Waldemar Zdun, Uwe Strembeck, Mark Faculty of Computer Science University of Vienna Austria Distributed Systems Group Vienna University of Technology Austria Institute for Information Systems WU Vienna Austria

ISBN: (纸本)9781450324694

Real-time collaborative Web applications allow a multitude of users to concurrently work on a shared document. Especially in business contexts it is often necessary to be able to precisely define and restrict who is allowed to edit which data field of such a shared document. Existing solutions for enforcing such access control restrictions typically rely on a central service, the policy decision point. However, for use cases with unreliable or limited connectivity, such as mobile devices, a permanent connection to this centralized policy decision point can not be guaranteed. To address this problem, we present a novel approach that includes methods for client-side enforcement of access control constraints for offline users, and merging of offline changes, that enables users to edit such access constrained shared documents offline. We propose a generic conflict detection and resolution approach that attempts to resolve merge conflicts that are inherent to access constrained documents automatically while prioritizing online users and maximizing the number of filled out data fields in a document. In addition, we discuss and evaluate our approach via a prototype implementation. Copyright 2014 ACM.

关键词： Authorization

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Performance comparison and optimization of channel coding for acoustic communication in shallow waters 9

Performance comparison and optimization of channel coding fo...

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9th ACM International Conference on Underwater Networks and systems, WUWNet 2014

作者： Uensal, Ufuk Moser, Steffen Slomka, Frank Institute of Embedded Systems/Real-Time Systems Faculty of Engineering and Computer Science Ulm University Albert-Einstein-Allee 11 Ulm89081 Germany

ISBN: (纸本)9781450332774

The coded communications using non-coherent orthogonal modulation and capacity-approaching binary channel codes namely low-density parity check code (LDPC) and turbo code are investigated in this paper with the focus on the main three characteristic effects of an underwater channel, namely, multi-path propagation, Doppler spread and ambient noise. Additionally, a new method was implemented and tested successfully to identify and eliminate the highamplitude noise from the received dataset.

关键词： Underwater acoustic communication

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Using restricted transactional memory to build a scalable in-memory database 14

Using restricted transactional memory to build a scalable in...

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9th ACM European Conference on computer systems, EuroSys 2014

作者： Wang, Zhaoguo Qian, Hao Li, Jinyang Chen, Haibo School of Computer Science Fudan University China Institute of Parallel and Distributed Systems Shanghai Jiao Tong University China Department of Computer Science New York University United States

ISBN: (纸本)9781450327046

The recent availability of Intel Haswell processors marks the transition of hardware transactional memory from research toys to mainstream reality. DBX is an in-memory database that uses Intel's restricted transactional memory (RTM) to achieve high performance and good scalability across multicore machines. The main limitation (and also key to practicality) of RTM is its constrained working set size: An RTM region that reads or writes too much data will always be aborted. The design of DBX addresses this challenge in several ways. First, DBX builds a database transaction layer on top of an underlying shared-memory store. The two layers use separate RTM regions to synchronize shared memory access. Second, DBX uses optimistic concurrency control to separate transaction execution from its commit. Only the commit stage uses RTM for synchronization. As a result, the working set of the RTMs used scales with the meta-data of reads and writes in a database transaction as opposed to the amount of data read/written. Our evaluation using TPC-C workload mix shows that DBX achieves 506,817 transactions per second on a 4-core machine. Copyright © 2007 by the Association for Computing Machinery, Inc.

关键词： Concurrency control

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