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Demonstration of Planar Geometry PIN Photodetectors with GeSi/Ge Multiple Quantum Wells Hybrid Intrinsic Region on a Ge-on-Insulator Platform

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ACS Applied Electronic Materials 2025年第11期7卷 5205-5216页

作者： Junhao Du Xuewei Zhao Yuanhao Miao Jiale Su Ben Li Xiangliang Duan Tianyu Dong Jiahan Yu Hongxiao Lin Yuhui Ren Bo Wang Tianchun Ye Henry H. Radamson Key Laboratory of Microelectronic Devices & Integrated Technology Institute of Microelectronics Chinese Academy of Sciences Beijing 100029 China；School of Integrated Circuits University of Chinese Academy of Sciences Beijing 100049 China Research and Development Center of Optoelectronic Hybrid IC Guangdong Greater Bay Area Institute of Integrated Circuit and System Guangzhou 510535 China Key Laboratory of Microelectronic Devices & Integrated Technology Institute of Microelectronics Chinese Academy of Sciences Beijing 100029 China；Research and Development Center of Optoelectronic Hybrid IC Guangdong Greater Bay Area Institute of Integrated Circuit and System Guangzhou 510535 China；School of Integrated Circuits University of Chinese Academy of Sciences Beijing 100049 China

In this article, the first demonstration of planar geometry Ge PIN short-wave infrared (SWIR) photodetectors (PDs) on a germanium-on-insulator (GOI) platform has been presented. The intrinsic layer Ge contains four Ge0.86Si0.14multiple quantum wells (MQWs). The structural characteristics, material quality, and interface integrity of the PDs were investigated by using high-resolution transmission electron microscopy (HR-TEM) and high-resolution X-ray diffraction (HR-XRD). The devices exhibited a 3.12 mA/cm2dark current density and a low bulk leakage current density of 0.94 mA/cm2at −1 V. The integration of tensile-strained GeSi/Ge MQWs significantly enhanced the responsivity while maintaining a relatively lower dark current density, thereby broadening the spectral response range to 1700 nm. The notably high responsivities at 1310 and 1550 nm are 0.99 and 0.78 A/W, respectively, corresponding to external quantum efficiencies (EQEs) of 93.7 and 62.4%. Furthermore, the optical confinement effect inherent to this type of GOI structure contributed to a pronounced enhancement in the responsivity across the O, E, S, and C bands, with a peak responsivity of 1.11 A/W at 1475 nm. These findings underscore the potential of CMOS-compatible GOI platforms with MQWs hybrid intrinsic regions for diversified optoelectronic applications. Additionally, the demonstrated planar geometry Ge PIN PDs on insulator substrates exhibit excellent prospects for high-resolution SWIR imaging, which pave the way for advancements in next-generation photonic and sensing technologies.

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Impact of gate length on the electrical characteristics of junctionless FDSOI strained SiGe channel p-FinFET

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Journal of Materials Science: Materials in Electronics 2025年第15期36卷

作者： Lin, Hongxiao Miao, Yuanhao Ren, Yuhui Zhang, Yongkui Zhang, Qingzhu Xiong, Wenjuan Yu, Jiahan Zhao, Xuewei Liang, Renrong Xu, Jun Ye, Tianchun Radamson, Henry H. Key Laboratory of Microelectronic Devices & Integrated Technology Institute of Microelectronics Chinese Academy of Sciences Beijing100029 China Research and Development Center of Optoelectronic Hybrid IC Guangdong Greater Bay Area Institute of Integrated Circuit and System Guangzhou510535 China School of Microelectronics University of Chinese Academy of Sciences Beijing100049 China School of Integrated Circuits Tsinghua University Beijing100086 China

In this work, we present the influence of structure design on the performance of novel fully depleted silicon-on-insulator (FDSOI) SiGe p-type FinFETs. The effects of Ge content, strain in the epitaxial SiGe channel and gate length (LG) on the device’s electrical characteristics are systematically studied. Among the studied SiGe compositions, Si0.75Ge0.25 exhibits superior performance over Si0.7Ge0.3, as the latter shows the increased defect density due to strain relaxation, degrading carrier transport and the overall device performance. The strain in the Si0.75Ge0.25 channel is tailored to be 0.65% according to the nano beam diffraction (NBD) results, which enhances carrier mobility and drive current (Ion). As the LG decreases from 500 to 30 nm, the device exhibits a well-balanced trade-off between high drive current and low leakage current, demonstrating the effectiveness of the proposed device structure, while the subthreshold swing (SS) shows a progressive deterioration with decreasing LG, reflecting the growing impact of short-channel effects and interface states. At LG = 30 nm, the drain current (Id), maximum transconductance (Gm, max), and Ion/Ioff ratio can reach up to 0.19mA/μm, 33.2μS/μm, and 6.9 × 105, respectively. These improvements were attributed to the enhanced hole mobility from strain engineering and the superior electrostatic control of the junctionless architecture. Our work provides valuable insights into the optimization of junctionless FDSOI FinFETs, enhancing their potential for low-power, high-performance semiconductor applications in the beyond Moore era. © The Author(s), under exclusive licence to Springer Science+Business Media, LLC, part of Springer Nature 2025.

关键词： FinFET

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A monolithic SiGe BiCMOS power amplifier for UHF RFID application

A monolithic SiGe BiCMOS power amplifier for UHF RFID applic...

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11th International Conference on Wireless Communications, Networking and Mobile Computing (WiCOM 2015)

作者： Ying Ruan Lei Chen Guang Zhong Faculty of Electronics & Information Engineering Shanghai University of Electric Power China Institute of Microelectronic Circuit & System East China Normal University Shanghai China

ISBN: (纸本)9781510821279

A monolithic power amplifier (PA) is designed and implemented for UHF RFID Reader. The presented PA is based on a 0.18 um SiGe BiCMOS process and its working frequency band is from 860 MHz to 960 MHz. It is a linear class AB type with two stages and all the biasing, the power and the matching circuits are on a single chip with the area of 1.1 mm × 0.9 mm. On-chip test results show that the small-signal gain S 21 is above 23 dB, the input return loss S 11 and the output return loss S 22 is less than -21 dB and -15 dB, respectively. Also the test result indicate the proposed PA has an output 1 dB compression point of 23.3 dBm, a PAE of 27% and a power gain of above 23 dB.

关键词： Fully Integrated Power Amplifier SiGe BiCMOS UHF RFID SiGe BiCMOS Power amplifiers Power gain dubnium decibel Ultrahigh frequencies matching circuit Clinical Test Result Frequency bands

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A high linearity CMOS up-conversion mixer for UHF RFID reader application

A high linearity CMOS up-conversion mixer for UHF RFID reade...

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International Conference on Solid-State and Integrated circuit Technology

作者： Jianhang Fan Chunqi Shi Runxi Zhang Institute of Microelectronic Circuit & System East China Normal University Shanghai China

ISBN: (纸本)9781479932849

A high-linearity double-quadrature direct up-conversion mixer implemented by IBM 0.18μm CMOS process is presented. The mixer is designed based on Gilbert cell with degeneration resistors which can improve its linearity performance. Simulation shows that the circuit achieves 8.5dBm output 1dB compression point at 50Ω, a -11.14dB conversion loss, an output noise of -150 dBc/Hz @ 3.6MHz offset and a -35dBc image rejection while drawing 30mA current from 3.3V power supply.

关键词： Mixers Radiofrequency identification Linearity Noise Radio frequency Radio transmitters

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A Q-band CMOS LNA with common source topology based on algorithmic design methodologies

A Q-band CMOS LNA with common source topology based on algor...

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International Conference on Solid-State and Integrated circuit Technology

作者： Sheng Chen Runxi Zhang Chunqi Shi Yanlin Shi Zongsheng Lai Institute of MicroelEctronic Circuit System East China Normal University Shanghai CHINA

ISBN: (纸本)9781479932849

This work presents a low-noise amplifier (LNA), based on algorithmic design methodologies in 0.13μm technology. Spiral inductors were used in the on-chip impedance matching networks, rather than transmission lines. This three-stage common source LNA achieves the minimum noise figure of 4.97 dB at 45 GHz with a compact chip size of 0.62 mm 2 (including all the testing pads). The 3-dB frequency bandwidth ranges from 42 to 50 GHz and the peak gain of 19 dB at 45 GHz. The whole circuit dissipates 27mW from 1.5-V supply.

关键词： CMOS integrated circuits CMOS technology Abstracts Transistors Microwave amplifiers Microwave FET integrated circuits Microwave integrated circuits

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A 15 GHz CMOS low phase noise VCO using coupled coplanar waveguide

A 15 GHz CMOS low phase noise VCO using coupled coplanar wav...

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IEEE International Conference on Computer Research and Development

作者： Huang, Long Yuan, Shengyue Zhang, Runxi Li, Wei Institute of Microelectronic Circuit and System East China Normal University Shanghai 200062 China State Key Laboratory of ASIC and System Fudan University Shanghai 201203 China

ISBN: (纸本)9781612848372

A 15 GHz voltage-controlled-oscillator (VCO) with coupled coplanar waveguide (CCPW) inductor for LC resonator is proposed in this work. Methods including optimization of varactors and CCPW are applied to minimize the supply voltage and current. The CCPW is fabricated with the second top metal layer to improve the quality factor and isolate noise from substrate. The VCO is implemented using IBM 90 nm CMOS technology. The measured operation frequency ranges from 14.62 GHz to 15.5 GHz, and the phase noise is -94.86 dBc/Hz at 1MHz offset from 15.5 GHz. The VCO core draws 9.13mA current from 1.5V power supply. The calculated FoM is 168. © 2011 IEEE.

关键词： Monolithic microwave integrated circuits

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A 2.4GHz monolithic SiGe power amplifier for Wireless-LAN transceiver

A 2.4GHz monolithic SiGe power amplifier for Wireless-LAN tr...

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2nd Asia Pacific Conference on Postgraduate Research in microelectronics and Electronics, PrimeAsia 2010

作者： Ruan, Ying Chen, Lei Liu, Yan-Hua Ran, Feng Lai, Zong-Sheng Institute of Microelectronic Circuit and System East China Normal University Shanghai China Faculty of Computer and Information Engineering Shanghai University of Electric Power Shanghai China Key Laboratory of Advanced Display and System Application Ministry of Education Shanghai University Shanghai China

ISBN: (纸本)9781424467372

A high-linearity power amplifier (PA) for 2.4GHz Wireless-LAN transceiver is presented. The PA is designed and implemented using a 0.18um SiGe BiCMOS process. An on-chip adaptive linearizer is comprised of a base-emitter diode of the bias transistor and a bypass capacitor with almost no increase in die area and no extra dc consumption. Besides the linearization function, the active biasing circuit is also temperature-insensitive with simple structure. Including all matching circuits and biasing circuits, the die area of the fully integrated PA is 1.2mm*1.1mm. Temperature simulation indicates the variation of power gain is less than 1.6dB from 20°C to 80°C. The second-order and third-order IMD are less than -30.9dBc and -34.5dBc when the output P1dB has been reached. With 3.3V supply, the PA achieves max P1dB of 23.2dBm and a power added efficiency (PAE)of 21.3%.

关键词： Power amplifiers

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A Fully Integrated SiGe BiCMOS Power Amplifier for 2.4GHz Wireless-LAN Application

A Fully Integrated SiGe BiCMOS Power Amplifier for 2.4GHz Wi...

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International Conference on Wireless Communications, Networking and Mobile Computing (WiCom)

作者： Ying Ruan Lei Chen Liang Tian Yan-hua Liu Zong-sheng Lai Faculty of Computer & Information Engineering Shanghai University of Electrical Power Shanghai China Institute of Microelectronic Circuit & System East China Jiao Tong University Shanghai China

A 2.4GHz power amplifier (PA) for Wireless-LAN application is designed and implemented in 0.18μm SiGe BiCMOS technology. Without any off-chip component or band wire for matching, the proposed power amplifier is fully integrated, which has a two-stage structure with temperature-insensitive biasing circuit to improve the linearity with almost no increase in die area. S parameter simulation results show that input impedance matching S11 and output impedance matching S22 is less than -13dB and -20dB respectively. The power amplifier has a power gain of 27.3dB, output 1dB compression point of 23.2dBm, and a power added efficiency(PAE) of 21.3%.The area of the die is 1148×1140μm 2 with all elements integrated on a single chip.

关键词： Power amplifiers Silicon germanium Linearity Power generation Radio frequency BiCMOS integrated circuits Power transistors

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A 2.4GHz monolithic SiGe power amplifier for Wireless-LAN transceiver

A 2.4GHz monolithic SiGe power amplifier for Wireless-LAN tr...

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Asia Pacific Conference on Postgraduate Research in microelectronics & Electronics (PrimeAsia)

作者： Ying Ruan Lei Chen Yan-hua Liu Feng Ran Zong-sheng Lai Faculty of Computer & Information Engineering Shanghai University of Electrical Power China Institute of Microelectronic Circuit & System East China Jiao Tong University China Key Laboratory of Advanced Display and System Application Ministry of Education Shanghai University Shanghai China

A high-linearity power amplifier (PA) for 2.4 GHz Wireless-LAN transceiver is presented. The PA is designed and implemented using a 0.18 um SiGe BiCMOS process. An on-chip adaptive linearizer is comprised of a base-emitter diode of the bias transistor and a bypass capacitor with almost no increase in die area and no extra dc consumption. Besides the linearization function, the active biasing circuit is also temperature-insensitive with simple structure. Including all matching circuits and biasing circuits, the die area of the fully integrated PA is 1.2 mm * 1.1 mm. Temperature simulation indicates the variation of power gain is less than 1.6dB from 20°C to 80°C. The second-order and third-order LMD are less than -30.9 dBc and -34.5 dBc when the output PI dB has been reached. With 3.3 V supply, the PA achieves max PldB of 23.2 dBm and a power added efficiency (PAE) of 21.3%.

关键词： Power amplifiers Silicon germanium Power generation Radio frequency Power transistors Metals BiCMOS integrated circuits

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Design and modeling of reconfigurable MEMS low pass filter

Design and modeling of reconfigurable MEMS low pass filter

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ICSICT-2006: 2006 8th International Conference on Solid-State and Integrated circuit Technology

作者： Cai, Miao Guo, Xing-Long Li, Yong Liu, Lei Zong-sheng, Lai Institute of Microelectronic Circuit and System East China Normal University Shanghai 200062 China

ISBN: (纸本)1424401615

This paper presents the design and modeling of a unit cell for reconfigurable microwave microelectro-mechanical systems (MEMS) low pass filters (LPF), with reconfigurable inductance and capacitance. Lumped elements are introduced here to approximate the characteristics of the distributed filters, and then optimization is performed to obtain the superior characteristics as needed. LPFs with arbitrary cut-off frequency between 10GHz to 30GHz can be optimized corresponding to this model. Using this prototype, the reconfigurable LPF has a cut-off frequency switching from 7.8GHz to 15.3GHz, with ripple below 2dB and out-of-band rejection better than 40dB in both states, which demonstrates the validation of the proposed model. © 2006 IEEE.

关键词： Low pass filters

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