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2014 12th IEEE International Conference on Solid-State and Integrated circuit Technology, ICSICT 2014

作者： Yan, Yiyu Liu, Baobao Zhang, Runxi Shi, Chunqi Ding, Yanfang Lai, Zongsheng Institute of Microelectronics Circuit and System East China Normal University Shanghai200062 China

ISBN: (纸本)9781479932962

A dynamic 4:1 divider suitable for mm-wave frequency synthesizers is presented. Periodical injection technique is utilized to improve high frequency performance of the divider. The center frequency of the divider can be tuned through biasing to cover wide locking range. Simulation results show that the division frequency is improved 3 GHz with the proposed periodical injection technique. The maximum operating frequency extends to 29 GHz while the minimum is 7 GHz for 0.13 um CMOS technology. The 4:1 divider is power efficient which consumes 12mW excluding output buffers. © 2014 IEEE.

关键词： Millimeter waves

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A 0.18μm CMOS LNA for UHF-RFID reader application

A 0.18μm CMOS LNA for UHF-RFID reader application

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ICSICT-2006: 2006 8th International Conference on Solid-State and Integrated circuit Technology

作者： Chen, Yuan-Ying Zhang, Run-Xi Shi, Chun-Qi Lai, Zong-Sheng Institute of Microelectronics Circuit and System East China Normal University Shanghai 200062 China

ISBN: (纸本)1424401615

CMOS technologies are widely exploited in the area of GHz RF circuits as well as in the area of baseband circuits. Accordingly, CMOS LNA is gaining its popularity from applications such as GSM, PCS, and WLAN. In this paper, a novel low power consumption and high gain LNA for UHF-RFID (ultra high frequency-radio frequency identification) reader is presented. Basic analysis is introduced using those equations derived. Using these analyses, the stack style single-end structure with LC resonator using on-chip spiral inductor is investigated. This LNA exhibits power gain about 20.4dB and noise figure of 1.6dB while drawing 1mA current from 1.8V supply voltage under TSMC 0.18μm RF-CMOS process. The reverse isolation is about -36.7 dB. © 2006 IEEE.

关键词： CMOS integrated circuits

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A fully integrated 5GHz balanced SiGe HBT power amplifier design

A fully integrated 5GHz balanced SiGe HBT power amplifier de...

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2nd International Conference on Networks Security, Wireless Communications and Trusted Computing, NSWCTC 2010

作者： Chen, Lei Ruan, Ying Lai, Zong-Sheng Institute of Microelectronics Circuit and System East China Normal University Shanghai 200062 China

ISBN: (纸本)9780769540115

a 5GHz balanced fully integrated Power Amplifier (PA) on a single chip has been designed in a 0.18 μm SiGe BiCMOS technology. An analysis show that the process featured by 60GHz characteristic frequency can largely improve power output performance, and the differential topology optimized linearity, power added efficiency (PAE) and large signal performance. At 5.5GHz frequency, with 3.3V voltage supply, the 3-stage PA exhibits an output 1dB compression point (OP1dB) of 18dBm, max output power of 22dBm and a PAE of 23% at 0dBm input. The results show that the PA well meets the 802.11a Wireless Local Area Network (WLAN) standards. Overall chip area is 0.9x2.2 mm2 © 2010 IEEE.

关键词： Power amplifiers

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A 0.8-2.5GHz wideband SiGe BiCMOS low noise amplifier with noise fiugre of 1.98-3.3dB

A 0.8-2.5GHz wideband SiGe BiCMOS low noise amplifier with n...

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2011 IEEE 9th International Conference on ASIC, ASICON 2011

作者： Hua, Lin Yan, Qiong Chen, Lei Zhang, Runxi Shi, Chunqi Lai, Zongsheng Institute of Microelectronics Circuit and System East China Normal University Shanghai 200062 China

ISBN: (纸本)9781612841908

This paper presents an optimized 0.8-2.5GHz low noise amplifier for wideband applications. Based on cascade structure, a shunt resistive feedback with an emitter degeneration inductor is used. Both low noise figure and high gain are achieved simultaneously. Measured results show that the proposed LNA has a maximum gain of 19.6dB at 0.8GHz and a minimum gain of 14.3dB at 2.5GHz. The noise figure varies from 1.98 to 3.3dB among the whole band. The overall power supply is 24mw at 3V supply and the occupied die area is only 0.4mm 2. © 2011 IEEE.

关键词： Low noise amplifiers

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A stack-mode dual-band voltage-controlled oscillator for multistandard wireless applications

A stack-mode dual-band voltage-controlled oscillator for mul...

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ICSICT-2006: 2006 8th International Conference on Solid-State and Integrated circuit Technology

作者： Li, Yong Jing, Yi-Ou Shen, Yi-Hao Lai, Zong-Sheng Institute of Microelectronics Circuit and System East China Normal University Shanghai 200062 China

ISBN: (纸本)1424401615

A stack-mode dual-band VCO, which can be applied to 802.11a/b/g and Bluetooth multi-standard zero-IF transceiver, is proposed with low power consumption of 12.22 mW and excellent phase noise performance of -126.2 and -120.1 dBc/Hz at 1MHz offset from 2.44 and 5.23-GHz carriers. The simulation is performed in Agilent ADS and this circuit with chip area of 1.18×0.67 mm2 will be implemented by 0.18-μm CMOS process. ©2006 IEEE.

关键词： Variable frequency oscillators

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Design, analysis, and implementation of analog complex filter for low-IF wireless LAN application

Design, analysis, and implementation of analog complex filte...

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Proceedings - 17th International Conference on VLSI Design, Concurrently with the 3rd International Conference on Embedded systems Design

作者： Teo, T. Hui Khoo, Ee-Sze Uday, Dasgupta Tear, Chin-Boon Institute of Microelectronics Intgd. Circuit and System Laboratory Singapore Science Park II Singapore 117685

The design and implementation of an analog complex filter for low-IF WLAN 802.11a receiver is described. An IF of 20MHz is chosen as a trade off between image-rejection and power consumption. The specified bandwidth is 20MHz. Baseband processing requires low group-delay variation in the received signal to meet bit error rate (BER) specification. This requires a design of high frequency, wide bandwidth and high attenuation filter. To resolve these issues, fifth-order complex transitional Bessel-Chebyshev filter is implemented to compromise between high attenuation and low group-delay variation. Measured results show the designed filter provides 30dB to 40dB image rejection and 18dB adjacent channel rejection, while keeping a low group-delay variation of below 6.0ns within the pass-band. High frequency and wide bandwidth filter also requires stringent design specification of the circuitries. Differential inverter transconductor is optimized for this continuous-time filter design. The complete filter including on-chip tuning circuit and bandgap consumes only 7.5mA with 1.8V single supply voltage. The circuit is fabricated using 0.18 μm, 6-metal-single-poly CMOS process.

关键词： Electric filters

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Implementation and optimization of A5-1 algorithm on Coarse-Grained Reconfigurable Cryptographic Logic Array 12

Implementation and optimization of A5-1 algorithm on Coarse-...

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2017 IEEE 12th International Conference on ASIC

作者： Min Liu YingJian Yan Wei Li Department of Microelectronics Zhengzhou Institute of Information Science and Technology STATE Key Laboratory of Fudan University Special Integrated Circuit and System

ISBN: (纸本)9781509066261;9781509066254

A5-1 algorithm is a stream cipher used to encrypt voice data in GSM,which needs to be realized with high performance due to real-time *** implementation on FPGA or ASIC can't obtain a trade-off among performance,cost and *** this aim,this paper introduces CGRCA to implement A5-1,and in order to optimize the performance and resource consumption,this paper proposes a resource-based path seeking(RPS) algorithm to develop an advanced *** results show that final optimal throughput of A5-1 implemented on CGRCA is 162.87 Mbps when the frequency is 162.87 MHz,and the set-up time is merely 87 cycles,which is optimal among similar works.

关键词： A5-1 CGRCA RPS adaptive algorithm throughput

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An Improved Ziggurat-Based Hardware Gaussian Random Number Generator 13

An Improved Ziggurat-Based Hardware Gaussian Random Number G...

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2016 13th IEEE International Conference on Solid-State and Integrated circuit Technology (ICSICT)

作者： Jianing Su Jun Han Advanced Circuit and System Lab Suzhou Institute of Nano-tech and Nano-Bionics Chinese Academy of Sciences ASIC & System State Key Lab Department of Microelectronics Fudan University

ISBN: (纸本)9781467397209

The Ziggurat algorithm is an efficient way for building a Gaussian random number generator(GRNG), which is useful in many scientific and engineering applications. As the classic ziggurat-based GRNG includes nonlinear operations in judging the wedge and tail regions, which is complicated and resource consuming. An improved ziggurat algorithm is proposed by optimizing the accepting model with piecewise linear fitting, replacing the nonlinear operations with linear ones. The improved GRNG works with a 33% decrease of resource and has no significant performance loss. In addition, the uniform random number generator(URNG) in GRNG is implemented by metastability-based ring oscillators with XOR trees, which is the state-of-the-art technique for generating true random numbers in fully digital ways. FPGA results show that the proposed GRNG generates good normal distribution samples with a smooth power spectrum.

关键词： ziggurat random number generator piecewise linear fitting metastability-based ring oscillators

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Modifying the Power and Performance of 2-Dimensional MoS_(2)Field Effect Transistors

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Research 2023年第3期2023卷 741-756页

作者： Fulin Zhuo Jie Wu Binhong Li Moyang Li Chee Leong Tan Zhongzhong Luo Huabin Sun Yong Xu Zhihao Yu College of Integrated Circuit Science and Engineering Nanjing University of Posts and TelecommunicationsNanjing 210023China Guangdong Greater Bay Area Institute of Integrated Circuit and System Guangzhou 510535China Institute of Microelectronics Chinese Academy of SciencesBeijing 100029China College of Electronic and Optical Engineering and College of Flexible Electronics(Future Technology) Nanjing University of Posts and TelecommunicationsNanjing 210023China

Over the past 60 years,the semiconductor industry has been the core driver for the development of information technology,contributing to the birth of integrated circuits,Internet,artificial intelligence,and Internet of *** technology has been evolving in structure and material with co-optimization of performance–power–area–cost until the state-of-the-art sub-5-nm ***-dimensional(2D)semiconductors are recognized by the industry and academia as a hopeful solution to break through the quantum confinement for the future technology *** the recent 10 years,the key issues on 2D semiconductors regarding material,processing,and integration have been overcome in sequence,making 2D semiconductors already on the verge of *** this paper,the evolution of transistors is reviewed by outlining the potential of 2D semiconductors as a technological option beyond the scaled metal oxide semiconductor field-effect *** mainly focus on the optimization strategies of mobility(μ),equivalent oxide thickness(EOT),and contact resistance(RC),which enables high ON current(Ion)with reduced driving voltage(Vdd).Finally,we prospect the semiconductor technology roadmap by summarizing the technological development of 2D semiconductors over the past decade.

关键词： overcome driving enable

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A fully integrated, highly linear SiGe BiCMOS class-AB power amplifier targeting 2.4GHz applications

A fully integrated, highly linear SiGe BiCMOS class-AB power...

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Asia Pacific Conference on Postgraduate Research in microelectronics & Electronics (PrimeAsia)

作者： Zhang, Shulin Su, Jie Chen, Lei Tian, Liang Zhou, Jin Ruan, Ying Liu, Shengfu Zhang, Wei Hua, Lin Ran, Feng Lai, Zongsheng Institute of Microelectronics Circuit and System East China Normal University Shanghai China Key Laboratory of Advanced Display and System Application Shanghai University Shanghai China

ISBN: (纸本)9781424467372

This paper presents a 2.4GHz fully integrated power amplifier based on 0.18μm SiGe BiCMOS technology for wireless local area network applications [1]. The power amplifier shows a 1 dB compression output power of 22.19dBm at an input power of 0.135dBm. A temperature-insensitive bias circuit is used in this PA design to improve the amplifier linearity. The total fabricated die size is about 1.5mm×1.2mm. The designed PA based on SiGe BiCMOS technology demonstrates a competitive linearity performance compared with GaAs, when considering the factors of cost and process complexity.

关键词： Power amplifiers

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