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Advanced Patterning Solutions (IWAPS), International Workshop on

作者： Jiaxin Lin Lisong Dong Taian Fan Xu Ma Rui Chen Yayi Wei a Integrated Circuit Advanced Process Center Institute of Microelectronics of Chinese Academy of Sciences b University of Chinese Academy of Sciences Beijing China a Integrated Circuit Advanced Process Center Institute of Microelectronics of Chinese Academy of Sciences Beijing China c Key Laboratory of Photoelectronic Imaging Technology and System of Ministry of Education of China School of Optics and Photonics Beijing Institute of Technology Beijing China Integrated Circuit Advanced Process Center Institute of Microelectronics of Chinese Academy of Sciences University of Chinese Academy of Sciences Beijing China

ISBN: (数字)9781728175775

ISBN: (纸本)9781728175782

Near-field calculation for thick mask is a fundamental task in lithography simulations. This paper proposes a fully convolution network (FCN) method to improve the efficiency of three-dimensional (3D) mask near-field calculation compared to the rigorous electromagnetic field (EMF) simulation methods. Taking into account the 3D mask effects, the network is trained based on a set of mask samples and the corresponding near-field data obtained by the EMF simulator. During the testing stage, the trained FCN is used to rapidly predict the diffraction near-field of the testing mask patterns. The performance of the proposed FCN approach is evaluated by simulations based on EUV lithography.

关键词： Solid modeling Extreme ultraviolet lithography Three-dimensional displays Convolution Diffraction Task analysis Testing

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Packaged and ESD protected low noise amplifier design

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Dianzi Qijian/Journal of Electron Devices 2006年第3期29卷 691-696页

作者： Xu, Yong-Sheng Tao, Yong-Gang Hong, Liang You, Shu-Zhen Li, Xiao-Jin Shi, Chun-Qi Lai, Zong-Sheng Institute of Microelectronics Circuit and System East China Normal University Shanghai 200062 China

The effects of the package and ESD protection on the performance of the low noise amplifier are studied. By detailedly deriving the equations of the input impedance, transconductance, voltage gain and noise figure, an inductive degeneration common emitter low noise amplifier which is used in an ultra high frequency receiver chip is designed. The designed chip is implemented in a generic low cost 0.8 μm BiC-MOS process, and packaged in an SOIC28 package. The fact that the on-board measured results are very similar with the discussed and simulated results verifies the LNA design and optimization methodologies described in this paper.

关键词： ESD protection effects Low noise amplifier (LNA). Packaging effects Radio frequency (RF)

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A Fully Integrated 0.35μm SiGe Power Amplifier Design

A Fully Integrated 0.35μm SiGe Power Amplifier Design

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2012 IEEE 11th International Conference on Solid-State and Integrated circuit Technology(ICSICT-2012)

作者： Qiong Yan Lin Hua Chun-Qi Shi Run-Xi Zhang Zong-Sheng Lai Institute of Microelectronics Circuit&System East China Normal University Engineering Research Center for Nanophotonics&Advanced Instrument Ministry of EducationEast China Normal University

A fully integrated high-linearity power amplifier targeting 5.5GHz is implemented in 0.35μm SiGe BiCMOS *** presented power amplifier schematic has a two-stage single-ended common-emitter structure with 3.3V voltage ... 详细信息

关键词： PAE BiCMOS m SiGe Power Amplifier Design A Fully Integrated 0.35

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Wide band injection-locked quadrature prescaler based on ring oscillators

Wide band injection-locked quadrature prescaler based on rin...

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International Conference on Solid-State and Integrated circuit Technology

作者： Zi-yan Chen Lei Chen He-liang Ma Zong-sheng Lai Wei-ping Jing Institute of Microelectronics Circuit & System East China Jiao Tong University Shanghai China Jiangsu Province Key Laboratory of ASIC Design Nantong University Nantong Jiangsu China

A wide locking range injection-locked prescaler based on CMOS ring oscillators in the 0.25-¿m CMOS process is described. The prescaler¿s free-running frequency is 1.47 GHz, and the locking range covers from ... 详细信息

ISBN: (纸本)9781424421855

关键词： Wideband Ring oscillators circuits Tail Transceivers CMOS process Frequency Energy consumption Batteries Negative feedback loops

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Application of a CFD Simulation on Spin Coating Process

Application of a CFD Simulation on Spin Coating Process

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Electronics Design Automation (ISEDA), International Symposium of

作者： Xinchang Wang Yun Wang Yansong Liu Yayi Wei Tianchun Ye Guangdong Greater Bay Area Institute of Integrated Circuit and System Guangzhou China Chinese Academy of Sciences Institute of Microelectronics Beijing China University of Chinese Academy of Sciences School of Integrated Circuits Beijing China

ISBN: (数字)9798350352030

ISBN: (纸本)9798350352047

In this study, a three-dimensional spin coating model has been built up to simulation the flow formation process of Lagrange droplets in photoresist coating process. Numerical calculation was performed by using the commercial computational fluid dynamics (CFD) package with a Reynolds-averaged N avier-Stokes (RANS) equation solver and a realizable $k$ - ε two-layer model. The effects of the spin speed, dispensed volume, solvent saturated vapor pressure, initial photoresist viscosity on the film thickness and uniformity have been examined with different spin coating process parameters and material parameters. The initial photoresist viscosity and saturation vapor pressure are important parameters that affect the average film thickness. The spin-coating process of a wetting recipe was simulated using the model and compared with an recipe without wetting. The wetting recipe involves spraying 2.5cc of PGMEA solvent during static conditions, followed by the addition of 1cc of Lagrange photoresist droplets within 4.8 seconds. In contrast, the recipe without wetting injects 2cc of droplets at low speed. At the completion of the entire recipe, the wetting recipe exhibits an improved average film thickness compared to the typical recipe, it shows that wetting recipe can realized the purpose of photoresist reduction.

关键词： Viscosity Solvents Solid modeling Computational fluid dynamics Computational modeling Spraying Resists

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Compound Sacrificial Layer Process for RF MEMS Applications

Compound Sacrificial Layer Process for RF MEMS Applications

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2009 3rd IEEE International Symposium on Microwave,Antenna,Progagation and EMC Technologies for Wireless Communications(第三届微波、天线、电波传播和EMC技术国际会议

作者： Yong-hua Zhang Chao Wang Wei-xia Ouyang Zong-sheng Lai Institute of Microelectronics Circuit & System East China Normal University Shanghai China

ISBN: (纸本)9781424440757

Compound sacrificial layer has been developed for RF membrane bridge switch in micro electro mechanical systems (MEMS) tunable filters. The compound sacrificial layer consisting of polyimide and positive photoresist is used to avoid drawbacks which will occur when only polyimide or positive photoresist is used as sacrificial layer for suspended membrane with large area. The wet etching and dry etching are used to remove positive photoresist and polyimide, respectively. And the results of baking and etching of sacrificial layer are improved. The time is also shortened for the complete removal of sacrificial layer.

关键词： MEMS RF switch compound sacrificial layer polyimide positive photoresist

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Degradation of SOI SRAMs at 25°C Operating Conditions

Degradation of SOI SRAMs at 25°C Operating Conditions

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Electronics Packaging Technology Conference (EPTC)

作者： K. Wang J. Gao C. Zeng B. Li G. Zhang S. Ma P. Sun C. Wang N. Hao J. Li H. Liu F. Zhao J. Luo Z. Han Key Laboratory of Silicon Device Technology Institute of Microelectronics Chinese Academy of Sciences Beijing China University of Chinese Academy of Sciences Beijing China Guangdong Greater Bay Area Institute of Integrated Circuit and System Guangzhou China

ISBN: (纸本)9781665416207

In this paper, a dynamic life evaluation test of $0.35\mu \mathrm{m}$ PD SOI SRAM is conducted at $250^{\circ}\mathrm{C}$ ambient temperatures. Experiments show that the SOI SRAMs can safely operate for more than 600 hours at $250^{\circ}\mathrm{C}$. Analysis of failed devices demonstrates that electro-migration effect and Kirkendall effect may be the direct causes of device degradation. And underlying leakage of the device will greatly accelerate the degradation of the metal interconnect and package, which needs to be improved in future work.

关键词： Degradation Performance evaluation Power supplies Random access memory Metals Integrated circuit interconnections Failure analysis

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Process and Tool Monitor and Diagnosis Based on Overlay Data and Modeling

Process and Tool Monitor and Diagnosis Based on Overlay Data...

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China Semiconductor Technology International Conference (CSTIC)

作者： Yi Tong Libin Zhang Yayi Wei Tianchun Ye Yun Wang Guangdong Greater Bay Area Institute of Integrated Circuit and System Guangzhou China Institute of Microelectronics of Chinese Academy of Sciences (IMECAS) Beijing China School of Integrated Circuits University of Chinese Academy of Sciences Beijing China Nanjing Chengxin Institute of IC Technology Nanjing China

The overlay plays an important role in chip manufacturing for all technology nodes, but controlling it becomes increasingly difficult when the process node is less than 7nm or the number of 3D layers exceeds 100. The primary challenge in overlay control arises from tool and process variation, which can have a significant impact on chip performance and yield. This paper presents a systematic review and analysis based on overlay data and modeling to monitor process and tool variations by exploring and discussing four critical issues related to overlay control: the overlay mark selection method, over-fitting diagnosis method, scanner tool monitoring method, and process grouping method. The selected methods and models can be applied in various areas, including process development, tool monitoring, feedback model selection, and lot grouping.

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Intelligent Data Directory Construction Based on Data Classification and Grading

Intelligent Data Directory Construction Based on Data Classi...

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Distributed Computing and Electrical circuits and Electronics (ICDCECE), IEEE International Conference on

作者： Xing Wen Zheng Wang Zhenyu Chen Yongwen Gong Zhenlin Huang Ning Wang Liuqi Zhao Jinwei Zhu Yuheng Zhang China Southern Power Grid Extra High Voltage Power Transmission Company Guangzhou China Beijing Smartchip Microelectronics Technology Company Limited Beijing China Zhengzhou Zhongke Institute of Integrated Circuit and System Application Zhengzhou China

This article proposes an intelligent data directory construction scheme aimed at supporting the design of ultra-high voltage converter stations. The scheme utilizes visual techniques such as knowledge graphs to analyze large-scale data in the power industry and establish a data classification and grading standard. Specifically, the scheme selectively identifies key or core data for association analysis to reduce data processing scale and improve the speed of the directory system. After determining the results of data classification and grading, the scheme employs machine learning algorithms to perform semantic analysis and reasoning on important/core data, providing recommended associated information. Additionally, the scheme selectively performs association analysis on data based on its sensitivity and importance level to reduce the impact of data analysis on system performance and ensure efficient operation. The intelligent data directory also automatically retrieves relevant data based on factors such as association, timeliness, and source, and provides recommended information resources to workers, thereby improving data availability and effectively reducing work pressure.

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Wide Band Injection-Locked Quadrature Prescaler Based on Ring Oscillators

Wide Band Injection-Locked Quadrature Prescaler Based on Rin...

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2008 9th International Conference on Solid-State and Integrated-circuit Technology

作者： Zi-yan Chen Lei Chen He-liang Ma Zong-sheng Lai Wei-ping Jing Institute of Microelectronics Circuit & System East China Normal University Engineering Research Center for Nanophotonics & Advanced Instrument Ministry of EducationEast China Normal University Nantong University Jiangsu Province Key Lab of ASIC Design

＜正＞A wide locking range injection-locked prescaler based on CMOS ring oscillators in the 0.25-μm CMOS process is ***’s free-running frequency is 1.47GHz,and the locking range covers from 1GHz to 2.4GHz with in-ph... 详细信息

关键词： Prescaler Injection-locked Technique Ring Oscillator Large Locking Range

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