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npj Unconventional Computing 2024年第1期1卷 1-9页

作者： Fei Wang Woyu Zhang Zhi Li Rui Bao Xiaoxin Xu Chunmeng Dou Dashan Shang Ning Lin Zhongrui Wang Key Lab of Fabrication Technologies for Integrated Circuits Institute of Microelectronics Chinese Academy of Sciences Beijing 100029 China Key Laboratory of Microelectronic Devices and Integrated Technology Institute of Microelectronics Chinese Academy of Sciences Beijing 100029 China University of Chinese Academy of Sciences Beijing 100049 China Department of Electrical and Engineering the University of Hong Kong Hong Kong China ACCESS - AI Chip Center for Emerging Smart Systems InnoHK Centers Hong Kong Science Park Hong Kong China School of Microelectronics Southern University of Science and Technology Shenzhen 518055 China

Similarity search is essential in current artificial intelligence applications and widely utilized in various fields, such as recommender systems. However, the exponential growth of data poses significant challenges in search time and energy consumption on traditional digital hardware. Here, we propose a software-hardware co-optimization to address these challenges. On the software side, we employ a learning-to-hash method for vector encoding and achieve an approximate nearest neighbor search by calculating Hamming distance, thereby reducing computational complexity. On the hardware side, we leverage the resistance random-access memory crossbar array to implement the hash encoding process and the content-addressable memory with an in-memory computing paradigm to lower the energy consumption during searches. Simulations on the MovieLens dataset demonstrate that the implementation achieves comparable accuracy to software and reduces energy consumption by 30-fold compared to traditional digital systems. These results provide insight into the development of energy-efficient in-memory search systems for edge computing.

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Random resistive memory-based deep extreme point learning machine for unified visual processing

arXiv

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arXiv 2023年

作者： Wang, Shaocong Gao, Yizhao Li, Yi Zhang, Woyu Yu, Yifei Wang, Bo Lin, Ning Chen, Hegan Zhang, Yue Jiang, Yang Wang, Dingchen Chen, Jia Dai, Peng Jiang, Hao Lin, Peng Zhang, Xumeng Qi, Xiaojuan Xu, Xiaoxin So, Hayden Wang, Zhongrui Shang, Dashan Liu, Qi Cheng, Kwang-Ting Liu, Ming Department of Electrical and Electronic Engineering The University of Hong Kong Hong Kong Key Laboratory of Microelectronic Devices & Integrated Technology Institute of Microelectronics Chinese Academy of Sciences Beijing100029 China ACCESS - AI Chip Center for Emerging Smart Systems InnoHK Centers Hong Kong Science Park Hong Kong University of Chinese Academy of Sciences Beijing100049 China Frontier Institute of Chip and System Fudan University Shanghai200433 China College of Computer Science and Technology Zhejiang University Zhejiang310027 China Department of Electronic and Computer Engineering The Hong Kong University of Science and Technology Hong Kong

Visual sensors, including 3D LiDAR, neuromorphic DVS sensors, and conventional frame cameras, are increasingly integrated into edge-side intelligent machines. Realizing intensive multi-sensory data analysis directly on edge intelligent machines is crucial for numerous emerging edge applications, such as augmented and virtual reality and unmanned aerial vehicles, which necessitates unified data representation, unprecedented hardware energy efficiency and rapid model training. However, multi-sensory data are intrinsically heterogeneous, causing significant complexity in the system development for edge-side intelligent machines. In addition, the performance of conventional digital hardware is limited by the physically separated processing and memory units, known as the von Neumann bottleneck, and the physical limit of transistor scaling, which contributes to the slowdown of Moore's law. These limitations are further intensified by the tedious training of models with ever-increasing sizes. In this study, we propose a novel hardware-software co-design, random resistive memory-based deep extreme point learning machine (DEPLM), that offers efficient unified point set analysis. Data-wise, the multi-sensory data are unified as point sets and can be processed universally. Software-wise, most weights of deep extreme point learning machines are exempted from training, which significantly reduce training complexity. Hardware-wise, nanoscale resistive memory not only enables collocation of memory and processing, mitigating the von Neumann bottleneck and the slowdown of Moore's law, but also leverages the inherent programming stochasticity for generating the random and sparse weights of the DEPLM, which also lessens the impact of read noise. We demonstrate the system's versatility across various data modalities and two different learning tasks. Compared to a conventional digital hardware-based system, our co-design system achieves 5.90×, 21.04×, and 15.79× energy efficiency improv

关键词： Cost reduction

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Design-Technology Co-Optimizations (DTCO) for General-Purpose Computing In-Memory Based on 55nm NOR Flash Technology

Design-Technology Co-Optimizations (DTCO) for General-Purpos...

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International Electron devices Meeting (IEDM)

作者： Yang Feng Bing Chen Jing Liu Zhaohui Sun Hongyang Hu Junyu Zhang Xuepeng Zhan Jiezhi Chen School of Information Science and Engineering Shandong University Qingdao China School of micro-nano electronics Zhejiang University Zhejiang Hangzhou China Key Laboratory of Microelectronic Devices and Integrated Technology Institute of Microelectronics of Chinese Academy of Sciences Beijing China Neumem Co. Ltd Hefei China

ISBN: (纸本)9781665425735

In this work, based on 55nm NOR flash technology, a general-purpose computing in-memory (CIM) architecture is proposed for the first time. By using a device-aware DTCO approach, a flash-based high-precision partial differential equation (PDE) solver is constructed with the 32-bit floating point (FP) calculation ability. Memory cells (4bit/cell) work at the quasi-saturation region to balance the performances and reliabilities, and the hot hole injection (HHI) is utilized to tune each cell individually (negative Vth shift) in the matrix array, showing ultra-fast operation speed (~10ns) and ultra-low power dissipation. Comprehensive reliability characterizations are also done, including retention, read disturb, random signal noise (RTN) and endurance. It is witnessed that the proposed flash-based 32-bit CIM architecture can conduct high precision calculations with a good tolerance to the cells' fluctuations.

关键词： Fluctuations Poisson equations Voltage measurement Voltage fluctuations Programming Common Information Model (computing) Arrays

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Deep Insights into the Failure Mechanisms in Field-cycled Ferroelectric Hf0.5Zr0.5O2 Thin Film: TDDB Characterizations and First-Principles Calculations

Deep Insights into the Failure Mechanisms in Field-cycled Fe...

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International Electron devices Meeting (IEDM)

作者： Wei Wei Weiqiang. Zhang Fei Wang Xiaolei Ma Qianwen Wang Pengpeng Sang Xuepeng Zhan Yuan Li Lu Tai Qing Luo Hangbing Lv Jiezhi Chen School of Information Science and Engineering Shandong University Qingdao China Key Laboratory of Microelectronic Devices and Integrated Technology Institute of Microelectronics of Chinese Academy of Sciences Beijing China

ISBN: (数字)9781728188881

ISBN: (纸本)9781728188898

To address the failure mechanisms in ferroelectric devices, this work presents a systematical study on Hf 0.5 Zr 0.5 O 2 -based ferroelectric memory. Firstly, by detail electrical characterizations of P-V and C-V curves in field-cycled devices, three dominant failure modes can be well distinguished. Then, by combining the TDDB measurements and first-principles calculations, it is found that, 1) the annealing temperature has large impacts on the initial defects concentrations while weakly affect the trap generation rate; 2) the breakdown paths take place mainly in the amorphous regions, which could generate reconfigurable filaments and cause RRAM properties; 3) temporary recovered ferroelectricity during cycling can be explained by considering the unstable breakdown paths generated at the grain boundary.

关键词： Temperature measurement Annealing Voltage measurement Capacitance-voltage characteristics Current measurement Failure analysis Weibull distribution

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A 1.3-µW −0.3/+0.27°C Inaccuracy Fully-integrated Temperature Sensor Based on a Pre-Charge Relaxation Oscillator for IoT applications

A 1.3-µW −0.3/+0.27°C Inaccuracy Fully-integrated Tempera...

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Asia-Pacific Conference on Microwave

作者： Yi Tan Zexue Liu Xiucheng Hao Zhengkun Shen Haoyun Jiang Fan Tian Junhua Liu Laboratory of Microelectronic Devices and Circuits (MOE) Institute of Microelectronics Peking University Beijing China

ISBN: (数字)9781728135175

ISBN: (纸本)9781728135182

This paper presents a CMOS fully-integrated temperature sensor based on a relaxation oscillator for IoT applications. To reduce power consumption, this sensor utilizes the half-period pre-charge compensation relaxation oscillator and uses a time-to-digital convertor (TDC) instead of analog-to-digital convertor (ADC) to count. Besides, the current distribution circuit is employed to improve temperature accuracy. The proposed sensor is implemented in 0.18 μm CMOS and occupies an area of 0.11 mm 2 . Measurement results show that the temperature sensor achieves an inaccuracy of -0.3/+0.27 °C across -15°C to 65°C after 2-point calibration. The chip consumes 1.3 μW at 27°C with a 650 mV voltage supply.

关键词： Temperature sensors Temperature measurement Oscillators Internet of Things Integrated circuits Calibration Radiofrequency identification

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Low Voltage Dual-Modulus Frequency Divider Based on Extended True Single-Phase Clock Logic

Low Voltage Dual-Modulus Frequency Divider Based on Extended...

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2018 IEEE International Conference on Electron devices and Solid State circuits, EDSSC 2018

作者： Wang, Wanlu Jia, Song Wang, Ziyi Pan, Tao Wang, Yuan Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University Beijing100871 China

ISBN: (纸本)9781538662342

Two low voltage dual-modulus frequency divider based on extended true single-phase clock (E-TSPC) logic are proposed. By reducing the number of serial transistors from VDD to GND, the proposed designs can effectively work at low voltage. Simulation results in SMIC 40nm technology show that the presented design I has better power and speed performance with lower supply voltage. Compared to the referenced designs, the presented design II can work at the lowest supply voltage with little loss of performance. © 2018 IEEE.

关键词： Computer circuits

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A novel strategy for GaN-on-diamond device with a high thermal boundary conductance

arXiv

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arXiv 2021年

作者： Mu, Fengwen Xu, Bin Wang, Xinhua Gao, Runhua Huang, Sen Wei, Ke Takeuchi, Kai Chen, Xiaojuan Yin, Haibo Wang, Dahai Yu, Jiahan Suga, Tadatomo Shiomi, Junichiro Liu, Xinyu High-Frequency High-Voltage Device and Integrated Circuits RandD Center Institute of Microelectronics Chinese Academy of Sciences Beijing100029 China Department of Mechanical Engineering The University of Tokyo Tokyo Bunkyo113-8656 Japan University of Chinese Academy of Sciences Beijing100049 China Key Laboratory of Microelectronic Devices and Integrated Technology Institute of Microelectronics Chinese Academy of Sciences Beijing100029 China Collaborative Research Center Meisei University Tokyo Hino-shi191-8506 Japan Integrated Circuit Advanced Process RandD Center Institute of Microelectronics of Chinese Academy of Sciences Beijing100029 China

To achieve high device performance and high reliability for the gallium nitride (GaN)-based high electron mobility transistors (HEMTs), efficient heat dissipation is important but remains challenging. Enormous efforts have been made to transfer a GaN device layer onto a diamond substrate with a high thermal conductivity by bonding. In this work, two GaN-diamond bonded composites are prepared via modified surface activated bonding (SAB) at room temperature with silicon interlayers of different thicknesses (15 nm and 22 nm). Before and after post annealing process at 800 oC, thermal boundary conductance (TBC) across the bonded interface including the interlayer and the stress of GaN layer are investigated by time-domain thermoreflectance and Raman spectroscopy, respectively. After bonding, the 15 nm Si interlayer achieved a higher TBC. The post-annealing significantly increased the TBC of both interfaces, while the TBC of 22 nm silicon interlayer increased greater and became higher than that of 15 nm. Detailed investigation of the microstructure and composition of the interfaces were carried out to understand the difference in interfacial thermal conduction. The obtained stress was no more than 230 MPa for both before and after the annealing, and this high thermal stability of the bonded composites indicates that the room temperature bonding can realize a GaN-on-diamond template suitable for further epitaxial growth or device process. This work brings a novel strategy of SAB followed by high-temperature annealing to fabricate a GaN-on-diamond device with a high TBC. © 2021, CC BY.

关键词： Gallium nitride

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Design of low-power high-speed dual-modulus frequency divider with improved MOS current mode logic

Design of low-power high-speed dual-modulus frequency divide...

引用

2018 IEEE International Conference on Electron devices and Solid State circuits, EDSSC 2018

作者： Wang, Wanlu Jia, Song Pan, Tao Wang, Yuan Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University Beijing100871 China

ISBN: (纸本)9781538662342

One design technique that aims to reduce power consumption of MOS current mode logic dual-modulus frequency divider is presented in this paper. With combinational logic transferred the proposed scheme can obtain high working frequency. By merging the first master latches of CML DFFs, the simplified structure can achieve lower power consumption. Circuit simulation of the proposed structure in 28nm CMOS technology shows a 21% reduction of power consumption over conventional scheme is achieved at frequency of 56GHz. © 2018 IEEE.

关键词： Electric power utilization

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Aligned monolayer MoS2 ribbons growth on sapphire substrate via NaOH-assisted chemical vapor deposition

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Science China Materials 2020年第6期63卷 1065-1075页

作者： Shike Hu Jing Li Xiaoyi Zhan Shuang Wang Longbiao Lei Yijian Liang He Kang Yanhui Zhang Zhiying Chen Yanping Sui Da Jiang Guanghui Yu Songang Peng Zhi Jin Xinyu Liu State Key Laboratory of Functional Materials for Informatics Shanghai Institute of Microsystem and Information TechnologyChinese Academy of SciencesShanghai 200050China Center of Materials Science and Optoelectronics Engineering University of Chinese Academy of SciencesBeijing 100049China Microwave Devices and Integrated Circuits Department Institute of MicroelectronicsChinese Academy of SciencesBeijing 100029China

This study reports the growth of aligned monolayer molybdenum disulfide(MoS2)ribbons on a sapphire substrate via NaOH-assisted chemical vapor *** length of MoS2 ribbon is up to 400μ*** MoS2 ribbon has excellent single crystal properties,a carrier mobility of^150 cm^2V^-1s^-1,and a optical response of 103 mA W^-1 at a wavelength of 550 *** growth model of MoS2 ribbons was *** reacts with MoO3 to form sodium molybdate droplets,which increase the fluidity of the molybdenum source on the substrate,realizing the vapor-liquid-solid growth of MoS2 on *** monolayer MoS2 ribbons have two kinds of arrangements on the sapphire substrate,one is the oriented growth affected by the interlayer van der Waals force and the lattice,and the other is the aligned growth constrained by the sapphire *** results promote the basic research and device applications of MoS2,and introduce a new way of synthesizing other one dimensional(1D)and 2D nanostructures.

关键词： MoS2 aligned ribbons vapor-liquid-solid step epitaxy

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A Novel High-speed FPGA-based True Random Number Generator Based on Chaotic Ring Oscillator

A Novel High-speed FPGA-based True Random Number Generator B...

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International Conference on ASIC

作者： Xinning Liu Song Jia Hanzun Zhang Institute of Microelectronics Peking University Beijing China Key Laboratory of Microelectronic Devices and Circuits Peking University Beijing China

This paper presents a novel true random number generator with entropy source based on swappable matrix feedback ring oscillator (SMFRO). The proposed SMFRO structure utilizes multiple feedback mechanism to produce reliable chaotic oscillation. Three SMFROs implemented on FPGA with different resource configurations are tested. All of them can pass chaotic oscillation and NIST tests. Proposed design can generate random bits at 500MHz without extra post-processing.

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