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A review for compact model of graphene field-effect transistors

Chinese Physics B 2017年第3期26卷 96-113页

作者：卢年端汪令飞李泠刘明 Key Laboratory of Microelectronic Devices & Integrated Technology Institute of Microelectronics Chinese Academy of Sciences Beijing 100029 China University of Chinese Academy of Sciences Beijing 100049 China Jiangsu National Synergetic Innovation Center for Advanced Materials (SICAM) Nanjing 210009 China

Graphene has attracted enormous interests due to its unique physical, mechanical, and electrical properties. Specially, graphene-based field-effect transistors （FETs） have evolved rapidly and are now considered as an option for conventional silicon devices. As a critical step in the design cycle of modem IC products, compact model refers to the development of models for integrated semiconductor devices for use in circuit simulations. The purpose of this review is to provide a theoretical description of current compact model of graphene field-effect transistors. Special attention is devoted to the charge sheet model, drift-diffusion model, Boltzmann equation, density of states （DOS）, and surface-potential-based compact model. Finally, an outlook of this field is briefly discussed.

关键词： two-dimensional material graphene field-effect transistor compact model

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Vector Vortex Beam Arrays: Multichannel Spatially Nonhomogeneous Focused Vector Vortex Beams for Quantum Experiments (Advanced Optical Materials 8/2019)

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Advanced Optical Materials 2019年第8期7卷

作者： Enliang Wang Lina Shi Jiebin Niu Yilei Hua Hailiang Li Xiaoli Zhu Changqing Xie Tianchun Ye Key Laboratory of Microelectronic Devices and Integrated Technology Institute of Microelectronics Chinese Academy of Sciences Beijing 100029 China University of Chinese Academy of Sciences Beijing 100049 China

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A compact SCR model using advanced BJT models and standard SPICE elements

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Science China(Information Sciences) 2016年第10期59卷 248-250页

作者： Jian CAO Jingya XU Yuan WANG Guangyi LU Xing ZHANG Key Laboratory of Microelectronic Devices and Circuits (Ministry of Education) Institute of MicroelectronicsPeking University School of Software & Microelectronics Peking University

Dear editor,The Silicon controlled rectifiers(SCR)are widely used to protect integrated circuits(ICs)from electrostatic discharge(ESD)and electrical overstress(EOS)damage[1].An accurate SCR model is highly desirable in on-chip ESD protection *** studies modeled SCRs by aggregating conventional bipolar junction transistor(BJT)models and adding extra physical models that conventional BJT models fail to support[2,3].However the auxiliary models are mostly complicated

关键词： SPICE SCR A compact SCR model using advanced BJT models and standard SPICE elements BJT

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Source/Drain Architecture Design of Vertical Channel Nanowire FET for 10nm and beyond 13

Source/Drain Architecture Design of Vertical Channel Nanowir...

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2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT)

作者： Gong Chen Ming Li Jiayang Zhang Yuancheng Yang Ru Huang Key Laboratory of Microelectronic Devices and Circuits Institute of MicroelectronicsPeking University

ISBN: (纸本)9781467397209

In this paper, a source/drain design for vertical channel nanowire FETs involving extension doping profile, spacer dielectric constant and spacer width is proposed and demonstrated by TCAD simulation. The results show that asymmetric graded lightly doped drain(AGLDD) exhibits very good SCE controllability and driving capability even with relatively large nanowire diameter. By adopting high-k spacer material and optimizing drain spacer width, preferable SCE immunity and higher overdrive current are achieved while parasitic capacitance can be maintained in an acceptable range. This scheme provides a feasible guideline for future low power vertical channel nanowire FETs design.

关键词： simulation FET Source/Drain Architecture Design of Vertical Channel Nanowire FET for 10nm and beyond

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Statistical Analysis on Performance Degradation of 90 nm bulk SiMOS devices Irradiated by Heavy Ions 13

Statistical Analysis on Performance Degradation of 90 nm bul...

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2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT)

作者： Zhexuan Ren Xia An Weikang Wu Xing Zhang Ru Huang Key Laboratory of Microelectronic Devices and Circuits Institute of MicroelectronicsPeking University

ISBN: (纸本)9781467397209

In this paper, the radiation response of 90 nm bulk Si MOS devices irradiated by heavy ions is experimentally studied. Due to the intrinsic random incident of heavy ions, different performance degradation is observed, such as threshold voltage shift, saturation current change and maximum transconductance degradation. These performance degradations may be attributed to the displacement damage in channel region, interface states at gate oxide interface and trapped charges in STI, which are generated by heavy ion irradiation. Furthermore, the statistical analysis on the performance degradation of 90 nm bulk Si MOS devices is also demonstrated *** results indicate that the performance variation of90 nm bulk Si MOS devices enlarges after heavy ion irradiation compared with un-irradiated ***, the standard variation of threshold voltage shift, DIBL shift and off-state leakage current degradation induced by heavy ion irradiation increases with the decrease of gate width, which should be paid more attention. The results may provide guideline for radiation-hardened design.

关键词： Estimation Field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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Improved Crystallinity of Ultra-thin Amorphous Film By 2D-limited Regrowth: Process and Characterization 13

Improved Crystallinity of Ultra-thin Amorphous Film By 2D-li...

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2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT)

作者： Yuancheng Yang Ming Li Gong Chen Hao Zhang Xiaoyan Xu Ru Huang Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University

ISBN: (纸本)9781467397209

The 2-D limited regrowth of α-Si is proposed to achieve larger grain size and smoother surface simultaneously with conventional rapid thermal annealing process. Transmission line method is carried at room temperature and 100 K temperature separately to confirm that the boundary scattering and ionization scattering are possibly suppressed by the capping layer method due to less grain boundary and trapped ionization centers.

关键词： Monolithic 3D integration Amorphous silicon Two Dimensional(2D) Recrystallization Capping layer

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Nanoscale Ge Fin Etching Using Inductively Coupled Plasma for Ge-based Multi-gate devices 13

Nanoscale Ge Fin Etching Using Inductively Coupled Plasma fo...

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2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT)

作者： Bingxin Zhang Xia An Yuxuan Xia Ming Li Meng Lin Peilin Hao Xing Zhang Ru Huang Key Laboratory of Microelectronic Devices and Circuits Institute of MicroelectronicsPeking University

ISBN: (纸本)9781467397209

In this paper, nanoscale germanium(Ge) fin etching with inductively coupled plasma(ICP) equipment by Cl/BCl/Ar gas is experimentally demonstrated. The impact of Cl/BCl/Ar gas ratio on etching induced Ge surface roughness, etch rate, sidewall steepness, uniformity and layout dependence are comprehensively investigated. The surface roughness is improved by increasing Ar flow rate. A nearly vertical Ge Fin is obtained by optimizing Cl/BCl/Ar gas ratio. By using silicon oxide as hard mask, 60nm-width Ge Fin array with height of 100 nm is experimentally illustrated with high uniformity of etch depth and Fin width. Therefore, this method shows great potential for Ge-based multi-gate device fabrication.

关键词： Estimation Field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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Investigation of current collapse mechanism of LPCVD Si3N4 passivated AlGaN/GaN HEMTs by fast soft-switched current-DLTS and CC-DLTFS 29

Investigation of current collapse mechanism of LPCVD Si3N4 p...

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29th International Symposium on Power Semiconductor devices and IC's, ISPSD 2017

作者： Wang, Xinhua Kang, Xuanwu Zhang, Jinhan Wei, Ke Huang, Sen Liu, Xinyu Key Laboratory of Microelectronic Devices and Integrated Technology Institute of Microelectronics of Chinese Academy of Sciences Beijing100029 China State Key Laboratory of Electronic Thin Films and Integrated Devices University of Electronic Science and Technology of China Chengdu610054 China

ISBN: (纸本)9781509051724

In this work, we investigated the current collapse mechanism of AlGaN/GaN high-electron mobility transistors (HEMTs) with LPCVD Si3N4 passivation. With newly developed fast soft-switched current-DLTS techniques, we achieved current acquisition within 100 ns after each stress pulse and with high sampling rate up to 5 MSa/s. A single trap level (∼66 meV) and capture cross section On (-1.05×10-20 cm-2) has been found within the AlGaN/GaN HEMTs surface. Moreover, this trap level is confirmed by low-temperature Constant-Capacitance Deep-Level Transient Fourier Spectroscopy (CC-DLTFS) measurement on GaN MIS-diode structure. Although this trap level is quite shallow, it can still lead to current collapse in LPCVD-SiNx-passivated AlGaN/GaN HEMTs due to the small On. © 2017 IEEJ.

关键词： Silicon compounds

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Positive Bias Temperature Instability Degradation of Buried InGaAs Channel nMOSFETs with InGaP Barrier Layer and Al2O3 Dielectric

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Chinese Physics Letters 2017年第5期34卷 101-105页

作者：王盛凯马磊常虎东孙兵苏玉玉钟乐李海鸥金智刘新宇刘洪刚 Key Laboratory of Microelectronics Devices & Integrated Technology Institute of Microelectronics Chinese Academy of Sciences Beijing 100029 High-Frequency High-Voltage Device and Integrated Circuits R&D Center Institute of Microelectronics Chinese Academy of Sciences Beijing 100029 Guangxi Experiment Center of Information Science Guilin University of Electronic Technology Guilin 541004 Microsystem and Terahertz Research Center China Academy of Engineering Physics Chengdu 610200

Positive bias temperature instability stress induced interface trap density in a buried InGaAs channel metaloxide-semiconductor field-effect transistor with a InCaP barrier layer and Al2O3 dielectric is investigated. Well behaved split C-V characteristics with small capacitance frequency dispersion are confirmed after the insertion of the InCaP barrier layer. The direct-current Id-Vg measurements show both degradations of positive gate voltage shift and sub-threshold swing in the sub-threshold region, and degradation of positive △Vg in the oncurrent region. The Id-Vg degradation during the positive bias temperature instability tests is mainly contributed by the generation of near interface acceptor traps under stress. Specifically, the stress induced aeceptor traps contain both permanent and recoverable traps. Compared with surface channel InCaAs devices, stress induced recoverable donor traps are negligible in the buried channel ones.

关键词： InGaAs Positive Bias Temperature Instability Degradation of Buried InGaAs Channel nMOSFETs with InGaP Barrier Layer and Al2O3 Dielectric MOSFET Al

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A Hysteretic Buck DC-DC Converter Achieving 90% Peak Efficiency with Light-load Current of 0.1-10 mA 13

A Hysteretic Buck DC-DC Converter Achieving 90% Peak Efficie...

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2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT)

作者： Jiameng Qu Xiucheng Hao Fan Yang Junhua Liu Huailin Liao Key Laboratory of Microelectronic Devices and Circuits (MOE) Institute of Microelectronics Peking University

ISBN: (纸本)9781467397209

A buck DC-DC converter with very high light load efficiency is presented in this paper. It introduces hysteretic control when the large output ripple problem is not critical, especially in light-load condition. Moreover, a fast-response zero current detector(ZCD) is adopted to make the converter work in discontinuous conduction mode(DCM). Due to hysteretic control extremely simplified the control circuits, the converter is divided into two independent loops, which further simplifies the optimization of power consumption. The proposed converter is fabricated in a standard 55 nm CMOS process. It converts 1.8-2.5 V battery voltage into a stable output voltage of 1 V, and offers 100μA to 10 mA light-load current output. The hysteretic converter achieves peak efficiency of 88.5% and 90%, with a supply voltage of 2.5 V and 1.8 V, respectively.

关键词： DCM A Hysteretic Buck DC-DC Converter Achieving 90 Peak Efficiency with Light-load Current of 0.1-10 mA

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