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7th IEEE International Nanoelectronics Conference, INEC 2016

作者： Zhang, Zhuo Zhang, Yacong Fair, Miaomiao Zhao, Meng Liu, Dahe Lu, Wengao Chen, Zhongjian Peking University Shenzhen Graduate School Shenzhen518055 China Key Laboratory of Microelectronic Devices and Circuits Institute of Micro and Nano Electronics Peking University Beijing100871 China Beida Information Research Tianjin300452 China

ISBN: (纸本)9781467389693

This paper presents a column-level 14-bit two-stage analog-to-digital converter (ADC) based on pseudo-differential operational amplifier, which is designed for the readout circuit of X-ray sensor array. This low-power hybrid ADC employs an incremental sigma-delta ADC and a cyclic ADC, achieving a good trade-off between accuracy and conversion speed. The two stages share the same analog circuit to reduce area and power consumption. A test chip is fabricated in 0.18μm CMOS technology. The hybrid ADC in each column is performed in parallel with power consumption of 218.813μW. The simulation result reveals the effective number of bits (ENOB) is 13.775 bits. © 2016 IEEE.

关键词： Operational amplifiers

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Artificial Synapses: Photoelectric Plasticity in Oxide Thin Film Transistors with Tunable Synaptic Functions (Adv. Electron. Mater. 12/2018)

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Advanced Electronic Materials 2018年第12期4卷

作者： Quantan Wu Jiawei Wang Jingchen Cao Congyan Lu Guanhua Yang Xuewen Shi Xichen Chuai Yuxin Gong Yue Su Ying Zhao Nianduan Lu Di Geng Hong Wang Ling Li Ming Liu Key Laboratory of Microelectronic Devices & Integrated Technology Institute of Microelectronics of Chinese Academy of Sciences Beijing 100029 China University of Chinese Academy of Sciences Beijing 100049 China Jiangsu National Synergetic Innovation Center for Advanced Materials (SICAM) Nanjing 211800 China Key Laboratory of Wide Band Gap Semiconductor Technology School of Advanced Materials and Nanotechnology Xidian University Xi'an 710071 China

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Aharonov-Bohm effect in monolayer black phosphorus (phosphorene) nanorings

arXiv

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arXiv 2017年

作者： Zhang, Rui Wu, Zhenhua Li, X.J. Chang, Kai SKLSM Institute of Semiconductors Chinese Academy of Sciences Beijing100083 China College of Materials Science and Opto-Electronic Technology University of Chinese Academy of Sciences Beijing100049 China Key Laboratory of Microelectronic Devices and Integrated Technology Institute of Microelectronics Chinese Academy of Sciences Beijing100029 China College of Physics and Energy Fujian Normal University Fuzhou350007 China

This work presents theoretical demonstration of Aharonov-Bohm (AB) effect in monolayer phosphorene nanorings (PNR). Atomistic quantum transport simulations of PNR are employed to investigate the impact of multiple modulation sources on the sample conductance. In presence of a perpendicular magnetic field, we find that the conductance of both armchair and zigzag PNR oscillate periodically in a low-energy window as a manifestation of the AB effect. Our numerical results have revealed a giant magnetoresistance (MR) in zigzag PNR (with a maximum magnitude approaching two thousand percent). It is attributed to the AB effect induced destructive interference phase in a wide energy range below the bottom of the second subband. We also demonstrate that PNR conductance is highly anisotropic, offering an additional way to modulate MR. The giant MR in PNR is maintained at room temperature in the presence of thermal broadening effect. Copyright © 2017, The Authors. All rights reserved.

关键词： Nanostructured materials

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Thermal effect and compact model in three-dimensional (3D) RRAM arrays

Thermal effect and compact model in three-dimensional (3D) R...

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International Conference on Simulation of Semiconductor Processes and devices (SISPAD)

作者： N. D. Lu Z. W. Zong P. X. Sun L. Li Q. Liu H. B. Lv S. B. Long M. Liu Key Laboratory of Microelectronic Devices & Integrated Technology Institute of Microelectronics of Chinese Academy of Sciences Beijing China

A physical and electro-thermal Compact model for thermal effect and crosstalk in 3D RRAM arrays has been firstly proposed. The simulation results show that the transient thermal effect will dominate reset process. The proposed model is based on 3D Fourier heat flow equation and electro-thermal analogy which can couple thermal network to its electrical schematic. The comparison between the Compact model simulation results and numerical simulation shows a good accuracy. The proposed electro-thermal model then was written in Verilog-A by using Spectre on Cadence platform and had been verified by using ANSYS software.

关键词： Three-dimensional displays Semiconductor process modeling Heating Solid modeling Numerical models Thermal analysis Mathematical model

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Deep Insights into Dielectric Breakdown in Tunnel FETs with Awareness of Reliability and Performance Co-Optimization

Deep Insights into Dielectric Breakdown in Tunnel FETs with ...

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IEEE International Electron devices Meeting

作者： Qianqian Huang Rundong Jia Jiadi Zhu Zhu Lv Jiaxin Wang Cheng Chen Yang Zhao Runsheng Wang Weihai Bu Wenbo Wang Jin Kang Kelu Hua Hanming Wu Shaofeng Yu Yangyuan Wang Ru Huang Key Laboratory of Microelectronic Devices and Circuits (MOE) Institute of Microelectronics Peking University Beijing 100871 China Semiconductor Manufacturing International Corporation (SMIC) Shanghai 201203 and Beijing 100176 China

ISBN: (纸本)9781509039036

The gate dielectrics reliability in Tunnel FETs (TFETs) has been thoroughly investigated for the first time, which is found to be the dominant device failure mechanism compared with bias temperature ins tability degradation, and is much worse than MOSFETs with the same gate stacks due to a new stronger localized dielectric field peak at gate/source overlap region. The non-uniform electric field of dielectric in TFET also leads to the different mechanisms between soft breakdown and hard breakdown failure. Moreover, dielectric-field-associated parameters are discussed in detail, showing an intrinsic trade-off between dielectrics reliability and device performance optimization caused by the positive correlation between dielectric field and source junction field. A new robust design consideration is further proposed for reliability and performance co-optimization, which is experimentally realized by a new TFET design with both dramatically improved performance and reliability, indicating its great potentials for ultralow-power applications.

关键词： Tunnel FETs Awareness Reliability

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A Combined Wafer Bonding Method using Spin-coated Water Glass Adhesive Layer and Spot Pressing Bonding Technique 13

A Combined Wafer Bonding Method using Spin-coated Water Glas...

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2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT)

作者： Yang Xu Shengkai Wang Yinghui Wang Dapeng Chen Honggang Liu Key Laboratory of Microelectronics Devices & Integrated Technology Institute of Micro Electronics of the Chinese Academy of Sciences Smart Sensing R&D Centre Institute of Micro Electronics of the Chinese Academy of Sciences High-Frequency High-Voltage Device and Integrated Circuits R&D Center Institute of Micro Electronics of the Chinese Academy of Sciences

A combined wafer bonding method consist of spot pressing bonding technique and water glass adhesive layer is proposed. The mechanism of water glass bonding is investigated, and the two major factors in this bonding me... 详细信息

ISBN: (纸本)9781467397209

关键词： wafer bonding water glass Spot Pressing Bonding surface energy voids formation

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A new static power clamp co-designed with input ESD protection circuit

A new static power clamp co-designed with input ESD protecti...

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International Conference on Solid-State and Integrated Circuit Technology

作者： Jian Wang Jian Cao Guangyi Lu Xing Zhang Yuan Wang School of Software and Microelectronics Peking University Beijing China Peking University Beijing Beijing CN Key Laboratory of Microelectronic Devices and Circuits (MoE) Peking University Beijing China

ISBN: (纸本)9781467397209

A new static power clamp circuit integrated with input ESD protection is proposed in this paper. By skillfully incorporating traditional input ESD protection, the proposed circuit replaces the protection resistor by the active switch and merging the signal control circuit into trigger circuit of static power clamp. The proposed circuit is a whole-chip ESD protection scheme that has a low leakage and the excellent ESD performance.

关键词： Electrostatic discharges Clamps Logic gates Switching circuits Stress MOS devices Leakage currents

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Memristors: Memristor with Ag‐Cluster‐Doped TiO2Films as Artificial Synapse for Neuroinspired Computing (Adv. Funct. Mater. 1/2018)

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Advanced Functional Materials 2018年第1期28卷

作者： Xiaobing Yan Jianhui Zhao Sen Liu Zhenyu Zhou Qi Liu Jingsheng Chen Xiang Yang Liu Key Laboratory of Optoelectronic Information Materials of Hebei Province Key Laboratory of Digital Medical Engineering of Hebei Province College of Electron and Information Engineering Hebei University Baoding 071002 P. R. China Key Laboratory of Microelectronic Devices and Integrated Technology Institute of Microelectronics Chinese Academy of Sciences Beijing 100029 P. R. China Department of Materials Science and Engineering National University of Singapore 9 Engineering Drive 1 Singapore 117575 Singapore Department of Physics National University of Singapore 2 Science Drive 3 Singapore 117542 Singapore

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New Insights into the Near-Threshold Design in Nanoscale FinFET Technology for Sub-0.2V Applications

New Insights into the Near-Threshold Design in Nanoscale Fin...

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IEEE International Electron devices Meeting

作者： Xiaobo Jiang Shaofeng Guo Runsheng Wang Yuan Wang Xingsheng Wang Binjie Cheng Asen Asenov Ru Huang Key Laboratory of Microelectronic Devices and Circuits (MOE) Institute of Microelectronics Peking University Beijing 100871 China Synopsys 11 Somerset place Glasgow G3 7JT U.K

ISBN: (纸本)9781509039036

Energy consumption has become the major concern of the IC industry. As a result, near-threshold-voltage (NTV) design has attracted a lot of attention for its superiority in energy efficiency. However, NTV design is faced with the key challenge - variability, especially for FinFET technology where device electrical FoMs are found to be strongly correlated. In this paper, new methodology of NTV design optimization for FinFET is proposed for the first time, and demonstrated based on silicon data. Significant improvements are achieved in the following three aspects: (1) Our newly proposed predictive compact variability models in all-region are accurately calibrated with experimental data, using a simple characterization method;(2) A new efficient approach for logic design space optimization is proposed based on a set of elaborately selected subthreshold FoMs, and the impacts of variation on energy efficiency, delay variation and failure probability are thoroughly investigated;(3) The conventional gate sizing method is also ameliorated specifically for FinFET NTV design. Based on silicon data, the proposed methodology is then demonstrated under V~(dd)=199mV and V_(dd)=145mV, targeting energy-efficiency priority and V_(dd) priority scenarios, respectively. This work provides helpful guidelines for FinFET variation-aware near-threshold design.

关键词： New Insights into Near-Threshold Design FinFET

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A Low-power 14-bit Two-stage Hybrid ADC for Infrared Focal Plane Array Detector

A Low-power 14-bit Two-stage Hybrid ADC for Infrared Focal P...

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2016 IEEE Information Technology,Networking,Electronic and Automation Control Conference(ITNEC 2016)

作者： Zhuo Zhang Yacong Zhang Miaomiao Fan Meng Zhao Dahe Liu Wengao Lu Zhongjian Chen Peking University Shenzhen Graduate School Key Laboratory of Microelectronic Devices and Circuits Institute of Micro & Nano ElectronicsPeking University Beida (Binhai) Information Research

ISBN: (纸本)9781467391955

this paper presents a low-power 14-bit hybrid incremental Σ-Δ/cyclic analog-to-digital converter(ADC) based on pseudo-differential operational amplifier, which is designed for the readout circuit of infrared focal plane array *** two-stage hybrid ADC employs an incremental sigma-delta ADC and a cyclic ADC, achieving a good trade-off between accuracy and conversion speed. The two stages share the same analog circuit to reduce area and power consumption. A common-mood feedback module is used to suppress the influence of charge injection, and the effectiveness is demonstrated by detailed theoretical analysis and simulation result. A test chip is fabricated in 0.18 μm CMOS technology. The hybrid ADC in each column is performed in parallel with power consumption of218.813 μW. The simulation result reveals the effective number of bits(ENOB) is 13.775 bits.

关键词： hybrid ADC incremental sigma-delta cyclic low power infrared array detector

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