An extensive and complete experimental investigation with a full layout design of the channel direction was carried out for the first time to clarify the orientation dependence of germanium p-channel metal-oxide-semic...
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An extensive and complete experimental investigation with a full layout design of the channel direction was carried out for the first time to clarify the orientation dependence of germanium p-channel metal-oxide-semiconductor field-effect transistors (PMOSFETs). By comparison of gate trans-conductance, drive current, and hole mobility, we found that the performance trend with the substrate orientation for Ge PMOSFET is (110)〉(111) ~ (100), and the best channel direction is (110)/[110]. Moreover, the (110) device performance was found to be easily degraded as the channel direction got off from the [ 110] orientation, while (100) and (111) devices exhibited less channel orientation dependence. This experimental result shows good matching with the simulation reports to give a credible and significant guidance for Ge PMOSFET design.
Nitrogen plasma passivation (NPP) on (111) germanium (Ge) was studied in terms of the interface trap density, roughness, and interfacial layer thickness using plasma-enhanced chemical vapor deposition (PECVD)....
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Nitrogen plasma passivation (NPP) on (111) germanium (Ge) was studied in terms of the interface trap density, roughness, and interfacial layer thickness using plasma-enhanced chemical vapor deposition (PECVD). The results show that NPP not only reduces the interface states, but also improves the surface roughness of Ge, which is beneficial for suppressing the channel scattering at both low and high field regions of Ge MOSFETs. However, the interracial layer thickness is also increased by the NPP treatment, which will impact the equivalent oxide thickness (EOT) scaling and thus degrade the device performance gain from the improvement of the surface morphology and the interface passivation. To obtain better device performance of Ge MOSFETs, suppressing the interfacial layer regrowth as well as a trade-off with reducing the interface states and roughness should be considered carefully when using the NPP process.
In this work, new design techniques that aim to reduce power consumption of true single-phase clock-based (TSPC) prescalers is presented. The structure of divide-by-4/5 frequency divider is simplified, and its perform...
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ISBN:
(纸本)9781479983926
In this work, new design techniques that aim to reduce power consumption of true single-phase clock-based (TSPC) prescalers is presented. The structure of divide-by-4/5 frequency divider is simplified, and its performance is compared with previous work to demonstrate the improvement. Simulation results show at least a 25% reduction of power consumption is achieved by the proposed unit. In the 32/33 dual modulus prescaler, a critical path cutting scheme is introduced to improve speed to the limit decided by the divide-by-4/5 unit.
A novel human body channel (HBC) energy harvesting scheme for body sensor networks (BSNs) is proposed in this paper. Human body channel is utilized innovatively as energy transmission medium to reduce the transmission...
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ISBN:
(纸本)9781479983926
A novel human body channel (HBC) energy harvesting scheme for body sensor networks (BSNs) is proposed in this paper. Human body channel is utilized innovatively as energy transmission medium to reduce the transmission loss dramatically and eliminate influence of shadow effect. Further, a high sensitivity and efficiency rectifier is presented by introducing an effective threshold compensation circuit. Experimental results of the energy harvesting scheme show that it can supply 2-μW power typically at -5 dBm transmitted power and up to 19.5-μW at +7 dBm transmitted power by 30 cm distance of human body channel. The sensitivity of the proposed rectifier is -22.5 dBm with 1-V output voltage. When offering 5-μA output current, the rectifier can achieve 25.87% efficiency. The rectifier is implemented in a standard 0.18-μm CMOS process and operating frequency is 145 MHz.
The silicon PIN radiation detectors are always used under high working voltages. The breakdown voltage improvement has been researched in this paper. The resistivity of the silicon is larger than 20,000 Ω cm and the ...
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This paper presents a 0.5-2GHz RF front-end with Series N-path Filter. With series 8-path filter applied, an ultimate rejection larger than 46 dB with 30 dB out-of-band rejection at 50 MHz offset is achieved. Dynamic ...
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ISBN:
(纸本)9781479983926
This paper presents a 0.5-2GHz RF front-end with Series N-path Filter. With series 8-path filter applied, an ultimate rejection larger than 46 dB with 30 dB out-of-band rejection at 50 MHz offset is achieved. Dynamic power consumption is saved due to small filter switch size compared with parallel structures. Utilizing a tunable narrow band LNA in front of series N-path filter, 3rd harmonic rejection exceeding 54 dB with robust to process variation is realized. These techniques improve the front-end's adjacent and far-end frequency selectivity in RF domain, relaxing mixer's linearity design pressure. Implemented in 65 nm CMOS process, the frontend achieves a NF of 2.6-5.7 dB and maximum gain of 46-60 dB at 0.5-2 GHz, consuming 18-26 mW from 1.2 V voltage supply and occupies an area of 0.56 mm~2.
A wide band radio frequency (RF) root-mean-square (RMS) power detector (PD) is presented in this paper. A CMOS rectifier with unbalanced source-coupled pairs and auxiliary capacitors is utilized to constitute the reve...
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ISBN:
(纸本)9781479983926
A wide band radio frequency (RF) root-mean-square (RMS) power detector (PD) is presented in this paper. A CMOS rectifier with unbalanced source-coupled pairs and auxiliary capacitors is utilized to constitute the reverse received signal strength indicator (reverse-RSSI) architecture as proposed power detector with operating frequency from 300 MHz to 10 GHz. The auxiliary capacitors are introduced to improve linearity at high input power dramatically. The power detector can be connected to power amplifier without directional coupler due to the capacitor attenuation array. Simulation results show that the maximum detection power is as high as +30 dBm and dynamic range reaches more than 42 dB with ±1 dB error. The proposed power detector is implemented in a standard 180nm CMOS process with 0.113 mm~2 core area. The supply voltage is 3.3 V, and its static power consumption is 0.55 mW.
The principles and application of Generation-Recombination (GR) noise spectroscopy will be outlined and illustrated for the case of traps in Ultra-Thin Buried Oxide Silicon-on-Insulator nMOSFETs and for vertical polyc...
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Temperature dependence of HCI degradation in SOI STI-pLDMOSFETs had been investigated by MR-DCIV method. The temperature-driven interface trap generation was clearly revealed under V gmax HCI and NBTI stress for sing...
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Temperature dependence of HCI degradation in SOI STI-pLDMOSFETs had been investigated by MR-DCIV method. The temperature-driven interface trap generation was clearly revealed under V gmax HCI and NBTI stress for single/multi-finger layout device. The self-heating-enhanced degradation was associated with the interface trap generation in channel and accumulation regions and shared NBTI degradation mechanism.
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