Temperature dependence of HCI degradation in SOI STI-pLDMOSFETs had been investigated by MR-DCIV method. The temperature-driven interface trap generation was clearly revealed under V gmax HCI and NBTI stress for sing...
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Temperature dependence of HCI degradation in SOI STI-pLDMOSFETs had been investigated by MR-DCIV method. The temperature-driven interface trap generation was clearly revealed under V gmax HCI and NBTI stress for single/multi-finger layout device. The self-heating-enhanced degradation was associated with the interface trap generation in channel and accumulation regions and shared NBTI degradation mechanism.
The interface trap generation under V gmax HCI stresses in pLDMOSFETs has been studied using non-destructive multi-region direct-current current-voltage (MR-DCIV) technique. Several times larger MR-DCIV degradation p...
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ISBN:
(纸本)9781479962624
The interface trap generation under V gmax HCI stresses in pLDMOSFETs has been studied using non-destructive multi-region direct-current current-voltage (MR-DCIV) technique. Several times larger MR-DCIV degradation per finger was observed for multi-finger devices. Folded-gate layout device suffered more self-heating induced degradation. Our study results reveal that those effects shared the similar trends and mechanism with NBTI degradation. The self-heating enhanced degradation in multi-finger devices was due to the higher temperature rise and less channel edge heat dissipation. The impact of device layout on the HCI degradation has also been investigated. Our results suggested that the unfolded device layout can reduce self-heating enhanced V gmax HCI degradation.
Due to latch-up issue,the main problem of silicon-controlled rectifier(SCR)for power supply clamps in on-chip ESD protection is its inherent low holding voltage,especially in high-voltage *** this paper,we proposed a ...
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Due to latch-up issue,the main problem of silicon-controlled rectifier(SCR)for power supply clamps in on-chip ESD protection is its inherent low holding voltage,especially in high-voltage *** this paper,we proposed a MOS-inside SCR(MISCR)showing nearly no snapback character and good ESD robustness,which is qualified for on-chip power clamp ESD *** stacked device achieves a series of triggering and holding voltage by altering the stacking number,which can also be used for the high voltage ESD power supply clamp applications.
A wide range delay-locked loop (DLL) based clock and data recovery (CDR) circuit including coarse and fine tune blocks is proposed in this paper. The coarse tune block adopts a time to digital converter and digital co...
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ISBN:
(纸本)9781479983926
A wide range delay-locked loop (DLL) based clock and data recovery (CDR) circuit including coarse and fine tune blocks is proposed in this paper. The coarse tune block adopts a time to digital converter and digital control delay line to widen the frequency capture range, reduce locking time and prevent the false locking problem. In the fine tune block, a novel phase detector combines the tasks of sampling and charge-pump using half rate clock. Starting-control circuit can ensure CDR takes full use of the delay range provided by voltage control delay line. Moreover, a fully analog DLL technique is applied to exploit the benefits of low skew and jitter performance. The simulation result shows the proposed CDR can cover a wide frequency range from 180.5Mbps to 8Gbps, while the peak-to-peak jitter of recovery clock is 2.7ps at 200Mbps and 1.06ps at 8Gbps. Fabricated in a 65nm CMOS process, this design dissipates 9.9mW and 22.9mW respectively at 200 Mbps and 8Gbps from a 1.2 V supply.
Ti/Al contacts deposited on p-type epilayer doped with Al at 2×10 19 cm -3 are reported. The current-voltage curves of Ti/Al contacts annealed at different temperatures from 800 to 1000 °C were measured, w...
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Ti/Al contacts deposited on p-type epilayer doped with Al at 2×10 19 cm -3 are reported. The current-voltage curves of Ti/Al contacts annealed at different temperatures from 800 to 1000 °C were measured, which provided the specific contact resistances (SCRs) of 6.59×10 -5 Ω/cm 2 and 7.81×10 -5 Ω/cm 2 after annealing at 900°C for 5min and 950°C for 2min, respectively. The microstructures of Ti/Al contact on P-type 4H-SiC were investigated by X-ray diffraction (XRD). The results of XRD show that the phases of Ti 3 SiC 2 was formed at the metal/SiC interface after annealing, which could be effective to ohmic contacts on P-type 4H-SiC. The quantitative phase analysis were also discussed, which show that the phase composition of Ti 3 SiC 2 is key factor for low resistance to P-type 4H-SiC. Moreover, simulations proved that the gradual Ti 3 SiC 2 ISL reduces or eliminates the effective barrier height at the metal/Ti 3 SiC 2 /p-type and may also contribute to low contact resistivity.
This paper studies the amplitude of random telegraph noise (RTN) caused by a single trap in the sili- con film of ultra-thin buried oxide (UTBOX) silicon-on-insulator (SOl) devices. The film-defect-related RTN w...
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This paper studies the amplitude of random telegraph noise (RTN) caused by a single trap in the sili- con film of ultra-thin buried oxide (UTBOX) silicon-on-insulator (SOl) devices. The film-defect-related RTN was identified and analyzed by low frequency noise measurement and time domain measurement. Emphasis is on the relative amplitude AID/ID, which is studied in the function of the front-gate, the back-gate and the drain-to-source biases. Interesting asymmetric or symmetric VDS dependence of switched source and drain are observed and sup- ported by calibrated Sentaurus simulations. It is believed the asymmetry of the VDs dependence of the switched source and drain is related to the lateral trap position along the source and drain.
The dynamics of electron transport in single-layer MoS2 is simulated by employing the single particle Monte Carlo method. Acoustic phonon scattering, optical phonon scattering and Frohlich scattering are taken into ac...
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The dynamics of electron transport in single-layer MoS2 is simulated by employing the single particle Monte Carlo method. Acoustic phonon scattering, optical phonon scattering and Frohlich scattering are taken into account. It is found that the electron mobility decreases from 806cm2 /V.s for a transverse electrical field of 103 Vim to 426/112 cm2 /V.s for a transverse electrical field of 105/107 Vim. Further detailed analysis on carrier dynamics reveals that the low field mobility is dominated by the acoustic phonon scattering while the role of optical phonon scattering is to relax the electron energy below the optical phonon energy by efficient energy relaxation through optical phonon emission. Only when the transverse electrical field is larger than 106 V/m, the mobility can be determined by the optical phonon scattering, leading to a strong mobility degradation.
This paper proposes a low-power precisely detecting method for electrical-cardiac signal and an efficient signal processing architecture. Traditionally, an impedance channel is designed separately as well as the ECG c...
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This paper proposes a low-power precisely detecting method for electrical-cardiac signal and an efficient signal processing architecture. Traditionally, an impedance channel is designed separately as well as the ECG channel to eliminate the effects of motion-artifact which means more power consumption. The baseline drift and power-line disturbance can also effects signal quality and should be well controlled. In this design, a couple of electrodes and the front-end circuit are reused for both ECG and impedance signal detecting, so that the power-consumption is significantly reduced. Experimental results show that with this front-end architecture, the baseline drift is also well controlled and the power-line effect is reduced. With the proposed digital signal processing method, the location of QRS complexes are precisely detected, which is crucial for medical purpose.
An ultra low power digital baseband processor for passive UHF RFID tag which is compatible with the protocol of Chinese local standard (840-845 MHz and 920-925 MHz) is presented in this paper. A highly reused register...
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An ultra low power digital baseband processor for passive UHF RFID tag which is compatible with the protocol of Chinese local standard (840-845 MHz and 920-925 MHz) is presented in this paper. A highly reused register bank and a low-cost sort algorithm are proposed to minimize the power consumption and several other low power techniques are adopted, including low supply voltage, clock gating, and minimum operation frequency. The processor is fabricated in SMIC 0.18 um standard CMOS process and consumes 358 nA at 0.6 V voltage supply according to measured results and occupies only 0.1 mm 2 area.
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