A phase interpolator(PI)-based clock data recovery(CDR)circuit for RapidIO application is presented,which avoids the coupled interference of *** the integration of a digital control cell,the complex and area consu...
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ISBN:
(纸本)9781467324748
A phase interpolator(PI)-based clock data recovery(CDR)circuit for RapidIO application is presented,which avoids the coupled interference of *** the integration of a digital control cell,the complex and area consumption has been reduced *** adaptive bandwidth PLL structure is adopted so that it can provide clocks of three frequencies while maintain a good jitter *** a 0.13um CMOS process,the circuit has a jitter of 11.2ps@3.125Gbps with a power consumption of 21.7mW under 1.2V,and the core circuit area is 0.16mm2.
A novel radio frequency single-dielectric-barrier-discharge atmospheric pressure plasma generator was designed and utilized to strip AZ9912 photo-resist(PR). Argon(Ar) and oxygen(O) were employed as the working ...
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A novel radio frequency single-dielectric-barrier-discharge atmospheric pressure plasma generator was designed and utilized to strip AZ9912 photo-resist(PR). Argon(Ar) and oxygen(O) were employed as the working gases under atmospheric pressure in ambient air. The PR stripping rate was measured as functions of time, input power, and the flow rates of the oxygen/argon. Optical Emission Spectroscopy(OES) was used to measure the optical emission spectra of the plasma to study the mechanism of PR stripping process. It is presumable that C-H bands were broken by high energy electron in the plasma and OH was generated in the process with the participation of O atom. Optical Microscope, Atomic Force Microscope(AFM) and Scanning Electron Microscope(SEM) were used to measure the surface of the silicon substrate after the stripping. It is proved that this kind of novel device could strip the AZ9912 PR effectively as high as 850nm/min, without residues and ion bombardment damage on the wafer substrate.
For the silicided GGnMOS as ESD protection device, the current localization in the n+ diffusion duo to the short contact spacing often degrades the ESD performance of the device. By enlarging the contact spacing, ball...
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A novel layout strategy for on-chip ESD protection application is presented to solve the non-uniformity turn-on phenomenon of multi-finger gate-grounded nMOS (GGnMOS). The multi-finger gates as well as drains and sour...
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In this paper, an efficient method to relax timing requirements of CRFF sigma-delta modulators has been proposed. A system optimization to circuit level design was finished. Class-C inverter was used to realize half d...
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For the silicided GGn MOS as ESD protection device, the current localization in the n+ diffusion duo to the short contact spacing often degrades the ESD performance of the device. By enlarging the contact spacing, bal...
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For the silicided GGn MOS as ESD protection device, the current localization in the n+ diffusion duo to the short contact spacing often degrades the ESD performance of the device. By enlarging the contact spacing, ballasting resistance is introduced to allow a more uniform current distribution. How the drain contact to gate spacing and contact to contact spacing influencing the ESD performance of the GGn MOS is investigated. We find that lengthening the contact to contact spacing can significantly improve the ESD performance of silicided GGn MOS.
A novel on-chip CMOS current sensor implemented by switched capacitors for a current - mode buck converter is presented in this paper. This proposed current sensing circuit does not need another sense MOSFET and a vol...
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A novel on-chip CMOS current sensor implemented by switched capacitors for a current - mode buck converter is presented in this paper. This proposed current sensing circuit does not need another sense MOSFET and a voltage-to-current and current-to-voltage transform circuit. We use the 0.35um DPTM CMOS process to design and simulate this circuit. Test result shows that the accuracy and the speed of the proposed current sensing circuit are high.
A low power high speed Readout Integrated Circuit(ROIC) design for 320 × 320 IRFPA is proposed in this paper. The ROIC operates as follows: after integration phase, voltages on column bus of odd rows and even row...
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A low power high speed Readout Integrated Circuit(ROIC) design for 320 × 320 IRFPA is proposed in this paper. The ROIC operates as follows: after integration phase, voltages on column bus of odd rows and even rows are read out alternately. And the results are sampled and stored alternately on two sample capacitors added at the output point of column CSA. When sample capacitor for odd row samples and holds data, sample capacitor for even row works as feedback capacitor of output buffer so that voltage stored on sample capacitor can be read out directly. In this design, each column has one low power charge amplifier, and output buffer's power is optimized. Besides, capacitance of sample capacitor is much larger than that of CSA's feedback capacitor, so the KTC noise is lower and the charge injection is suppressed while the output range is not impaired. This design is also applicable to window readout. The readout speed can reach 8MHz with power consumption lower than 50mW. A 320 × 320 ROIC with pixel size of 30 × 30 μm 2 has been designed and fabricated with a 0.35 μm DPTM CMOS process under 5v supply voltage.
A silicon-controlled rectifier (SCR) device for on-chip ESD protection is proposed. The Anode pad of the device is directly connected to die drain of the embedded nMOS crossing the N-well P-substrate junction of the n...
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A silicon-controlled rectifier (SCR) device for on-chip ESD protection is proposed. The Anode pad of the device is directly connected to die drain of the embedded nMOS crossing the N-well P-substrate junction of the nMOS to achieve a high holding current. Thus, latch-up immune current of SCR type ESD protection device is achieved by this method.
Using an auxiliary quantizer before unity-STF SDM, a novel 3 rd -order dual-quantizer SDM with extended dynamic range is presented. With hybrid distributed feedback & feedforward paths and an internal feedforward ...
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Using an auxiliary quantizer before unity-STF SDM, a novel 3 rd -order dual-quantizer SDM with extended dynamic range is presented. With hybrid distributed feedback & feedforward paths and an internal feedforward path, a novel low-distortion 3 rd -order SDM with simple adder before quantizer is proposed as the unity-STF SDM. Simulations show their perfect immunity to non-idealities.
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