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A Comprehensive Study on Schottky Barrier Nanowire Transistors (SB-NWTs):Principle,Physical Limits and Parameter Fluctuations

A Comprehensive Study on Schottky Barrier Nanowire Transisto...

引用

2008 9th International Conference on Solid-State and Integrated-Circuit Technology

作者： Liangliang Zhang Zhaoyi Kang Runsheng Wang Ru Huang Key Laboratory of Microelectronic Devices and Circuits Institute of MicroelectronicsPeking University

P-type Schottky barrier nanowire transistors （p-SB-NWTs） are computational studied in this paper. We analyzed the working principle and physical limits on their performance in *** impact of Schottky contact of SB-NWTs on the current drivability,gate control and RF performance are studied comparing with conventional silicon nanowire transistors（SNWTs）.It is pointed out that the inferior performance of SB-NWTs can not be solved by changing the S/D or channel *** the other hand,small V_t,F_t and on-off ratio fluctuation caused by process variation on channel diameter are observed,which is an advantage of SB-NWTs.

关键词： A Comprehensive Study on Schottky Barrier Nanowire Transistors Principle,Physical Limits and Parameter Fluctuations SB-NWTs

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A Cost-Efficient 12-Bit 20Msamples/s Pipelined ADC

A Cost-Efficient 12-Bit 20Msamples/s Pipelined ADC

引用

2008 9th International Conference on Solid-State and Integrated-Circuit Technology

作者： Cao Junmin Chen Zhongjian Lu Wengao Zhao Baoying Key Laboratory of Microelectronic Devices and Circuits Institute of MicroelectronicsPeking University

A 12-bit 20MS/s cost-efficient pipelined analog-digital converter is presented.A dedicated first stage is proposed to eliminate the need of front-end SHA. Passive capacitor error-averaging technique(PCEA) and opamp sharing scheme are employed to achieve high resolutions and low power and *** offset and 1/f noise of Opamp is reduced by interchanging the polarity of input and output of Opamp during different clock *** with 0.5um CMOS technology,the ADC dissipates 65mw from a 5V supply,and achieves a peak SNDR of 70.1dB with a 1MHz full-scale sine input at 20MS/s.

关键词： A Cost-Efficient 12-Bit 20Msamples/s Pipelined ADC SHA

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Structure and Magnetic Properties of Co-doped TiO2 Nanotubes by Aqueous Solution Method

Structure and Magnetic Properties of Co-doped TiO2 Nanotubes...

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2008 9th International Conference on Solid-State and Integrated-Circuit Technology

作者： A-bo Zheng Yan Li Yi Wang Lei Sun Li-feng Liu De-dong Han Jin-feng Kang Xing Zhang Ru-qi Han Key Laboratory of Microelectronic Devices and Circuits Institute of MicroelectronicsPeking University

The Co-doped titanium dioxide nanotubes were synthesized via the aqueous solution *** hydrogenation,room temperature ferromagnetism (RTFM) was found in the cobalt doped titanium dioxide nanotubes at 300k by the vibrate sample magnetometer. As the concentration of cobalt increased,the observed ferromagnetism became *** X-ray diffraction, scanning electron microscopy,high-resolution transmission electron microscopy and energy dispersive X-ray spectroscopy were performed and excluded the existence of cobalt ***,the magnetic ions and oxygen vacancies induced by hydrogenation contribute to the observed ferromagnetism at 300K.

关键词： [IEEE keyword]Scanning electron microscopy Saturation magnetization Magnetic hysteresis Powders Titanium Cobalt Nanotubes

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Low Power Folding/Interpolating ADC with a Novel Dynamic Encoder Based on ROM Theory

Low Power Folding/Interpolating ADC with a Novel Dynamic Enc...

引用

2008 9th International Conference on Solid-State and Integrated-Circuit Technology

作者： Jilei Yin Yuan Wang Song Jia Zhen Liu Key Laboratory of Microelectronic Devices and Circuits Institute of MicroelectronicsPeking University

A 6-bit 200Msps Folding/Interpolating analog to digital converter(ADC) with a novel dynamic encoder based on Rom theory is *** Precharge & Evaluate dynamic circuit is employed in the novel encoder and the bit synchronization logic to achieve high speed and reduce power *** in SMIC 0.35um digital CMOS process,the whole ADC consumes only 35mW at a 3.3V voltage supply.

关键词： ADC MSB Low Power Folding/Interpolating ADC with a Novel Dynamic Encoder Based on ROM Theory

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A low power high speed ROIC design for 1024×1024 IRFPA with novel readout stage

A low power high speed ROIC design for 1024×1024 IRFPA with...

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IEEE Conference on Electron devices and Solid-State circuits

作者： Chang Liu Wengao Lu Zhongjian Chen Haimei Bian Lijiu Ji Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University

A low power high speed Read-Out Integrated Circuit (ROIC) for a short-wave Infra-Red Focal Plane Array (IRFPA) is designed as a prototype for 1024 times 1024 image system. Ripple integration and readout scheme as well as highly efficient power management are introduced to this design in order to decrease total power. To further increase the readout speed while decrease the power dissipation, a novel readout stage is proposed and adopted in this circuit. By using the new structure, the ROIC achieves a data rate of 10 M/s per channel, with the total power dissipation of 56 mW.

关键词： Power dissipation CMOS logic circuits Logic arrays Detectors Capacitors Power amplifiers Prototypes Logic devices Cooling Timing

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Impact of Gate Misalignment on the Performance of Dopant-Segregated Schottky Barrier MOSFETs

Impact of Gate Misalignment on the Performance of Dopant-Seg...

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2008 9th International Conference on Solid-State and Integrated-Circuit Technology

作者： Lang Zeng Xiao Yan Liu Gang Du Jin Feng Kang Ru Qi Han Key Laboratory of Microelectronic Devices and Circuits Institute of MicroelectronicsPeking University

The impact of gate misalignment on the performance of dopant-segregated Schottky Barrier MOSFET(DS SBTs) and on the carrier transport is investigated by Monte Carlo *** simulation results show that gate misalignment with dopant-segregated structure(DSS) has less significant impact on drain current than that without *** influence of gate misalignment with DSS becomes notable only when drain voltage is high enough,while gate misalignment without DSS affects drain current always no matter how much drain voltage *** carrier transport,our results demonstrate that maximal velocity at source side of DS SBTs without gate misalignment shows saturation,while saturation doesn't exist in DS SBTs with gate misalignment.

关键词： DSS Impact of Gate Misalignment on the Performance of Dopant-Segregated Schottky Barrier MOSFETs

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Characteristics of sub-100nm Ferroelectric Field Effect Transistor with High-k Buffer Layer

Characteristics of sub-100nm Ferroelectric Field Effect Tran...

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2008 9th International Conference on Solid-State and Integrated-Circuit Technology

作者： Rui Jin Yuncheng Song Min Ji Honghua Xu Jinfeng Kang Ruqi Han Xiaoyan Liu Key Laboratory of Microelectronic Devices and Circuits Institute of MicroelectronicsPeking University

The simulation work is carried out using two dimension device simulator to investigate the characteristics of sub-100nm ferroelectric field effect transistor(FeFET) with high-k material as the buffer *** configurations of gate stack are simulated and *** is shown that the structure of double-layer buffer can improve the device performance *** important issues for FeFET scaling down are also discussed in this paper.

关键词： Buffer Characteristics of sub-100nm Ferroelectric Field Effect Transistor with High-k Buffer Layer

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A Dual Loop Dual VCO CMOS PLL Using a Novel Coarse Tuning Technique for DTV

A Dual Loop Dual VCO CMOS PLL Using a Novel Coarse Tuning Te...

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2008 9th International Conference on Solid-State and Integrated-Circuit Technology

作者： Congyin Shi Huaizhou Yang Huiling Xiao Junhua Liu Huailin Liao Key Laboratory of Microelectronic Devices and Circuits Institute of MicroelectronicsPeking University

A CMOS phase-locked loop（PLL） which synthesizes frequencies between 474 and S58 MHz in steps of lMHz and settles in less than 180μs is *** PLL can be implemented as a sub-circuit for a frequency synthesizer which serves for UHF Digital-TV receiver. To realize fast loop settling,integer-N architecture that work with 1 MHz reference frequency is implemented and a novel adaptive frequency calibration（AFC） of programmable dichotomizing coarse tuning technology is *** novel AFC structure uses pulses of 2~n times of the PFD's reference frequency for counting and *** multi-band voltage controlled oscillators,which cover 866 to 1468 MHz and 1282 to 1892 MHz separately,are implemented so as to reduce VCO output noise and power consumption by reducing VCO gain on each frequency turning curse.I/Q carriers are generated by VCO output divided by *** in 0.18-μm CMOS technology,the PLL achieves phase noise of less than - 132dBc/Hz at 1.45 MHz offset.

关键词： phase-locked loops adaptive frequency calibration dual VCO phase noise dual loop

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Investigations on Proton-Irradiation-Induced Spacer Damage in Deep-Submicron MOSFETs

Investigations on Proton-Irradiation-Induced Spacer Damage i...

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2008 9th International Conference on Solid-State and Integrated-Circuit Technology

作者： Shoubin Xue Pengfei Wang Ru Huang Dake Wu Yunpeng Pei Wenhua Wang Xing Zhang Key Laboratory of Microelectronic Devices and Circuits Institute of MicroelectronicsPeking University

In this paper,we have focused our attention on DC characteristics degradation of 0.18μm MOSFETs after 10-MeV proton *** is shown that the threshold voltage shift,the transconductance degradation and the saturation drain current decrease are lager in PMOSFETs,while small effects are exhibited in *** the analysis,it is concluded that the basic damage mechanism is not ascribed to the gate oxide and the *** origin of the observed changes is due to the damage in spacer oxides of the *** mechanism involved is that the energetic protons incident on the spacer region lose their energy to displace the atoms, give rise to many defects,and create a disordered region(displacement damage region),where many defects and traps can capture positive charges to make the static characteristics ***,it is pointed out that the sidewalls are one of sensitive regions for irradiation hardness.

关键词： NMOSFET Investigations on Proton-Irradiation-Induced Spacer Damage in Deep-Submicron MOSFETs

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A Low Power ROIC Design for 1024×1024 IRFPA

A Low Power ROIC Design for 1024×1024 IRFPA

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2008 9th International Conference on Solid-State and Integrated-Circuit Technology

作者： Chang Liu Wengao Lu Zhongjian Chen Jing Li Yacong Zhang Lijiu Ji Key Laboratory of Microelectronic Devices and Circuits Institute of MicroelectronicsPeking University

A low power Read-Out Integrated Circuit(ROIC) for a short-wave Infra-Red Focal Plane Array(IRFPA) is designed as a prototype for 1024×1024 image *** integration and readout scheme as well as highly efficient power management is introduced to this design in order to decrease total power dissipation. To overcome the charge sharing problem caused by this low power readout scheme,novel low input capacitance column amplifier is *** Data rate is about 10M/s per channel,with a total power dissipation of 56mW.

关键词： IRFPA A Low Power ROIC Design for 1024

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