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A 900MHz UHF RFID reader transceiver in 0.18μm CMOS technology

A 900MHz UHF RFID reader transceiver in 0.18μm CMOS technol...

引用

International Conference on Solid-State and Integrated Circuit Technology

作者： Le Ye Huailin Liao Fei Song Jiang Chen Huilin Xiao Ruiqiang Liu Junhua Liu Xinan Wang Yangyuan Wang Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University China

ISBN: (纸本)9781424421855

This paper presents a UHF band (840 MHz~925 MHz) RFID reader transceiver design for the protocols of EPC Class-1 Gen-2 and ISO/IEC 18000-6C. The architecture and modules for the proposed transceiver are described and implemented in a standard 0.18 μm CMOS process. To suppress the leakage signal from transmitter to receiver, directional coupler and leakage cancellation circuit are introduced in the transceiver. A mixer with common-gate capacitor-cross-coupled input stage and vertical NPN switching stage is introduced to satisfy wideband matching and reduce 1/f noise corner. The transceiver, with an on-chip power-amplifier (PA) driver to drive off-chip PA, supports DSB-ASK, SSB-ASK and PR-ASK modulation schemes. A sigma-delta PLL is also implemented for 250 kHz channel hopping. Measurement results are given. Mixer achieves -8dBm P1 dB and 6.25 dB noise figure, phase noise of PLL is -127 dBc/Hz @ 1 MHz offset and settling time of channel hopping is within 30 μs. Settling time of killing leakage is less than 15 μs. The sensitivity of receiver can be -81dBm @ 40 kHz link frequency (LF). The total silicon area of the transceiver is 13 mm 2 , and draws 75 mA for 1.8 V supply voltage.

关键词： CMOS technology Radiofrequency identification Transceivers Phase locked loops Protocols ISO standards IEC standards CMOS process Transmitters Directional couplers

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Novel structural Ti/Al-based ohmic contacts on AlGaN/GaN heterostructures

Novel structural Ti/Al-based ohmic contacts on AlGaN/GaN het...

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International Conference on Solid-State and Integrated Circuit Technology

作者： Zhihua Dong Jinyan Wang Min Yu Yilong Hao C. P. Wen Yangyuan Wang Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University China

ISBN: (纸本)9781424421855

To improve the performances of ohmic contacts for GaN devices, a novel multilayer Ti/Al-based metal scheme (Ti/Al/Ti/Al/Ti/Al/Ti/Al/Ni/Au) on undoped AlGaN/GaN heterostructures was employed. A contact with ¿c (specific contact resistance) of 8.74E-07 ¿·cm2, Rc of 0.22 ¿·mm was demonstrated. Ohmic contacts with the novel metal structure were measured with I-V, SEM, HRTEM to show their properties. The results showed that ohmic contacts with novel structures have better surface morphology and proposed thermal stability than those using conventional Ti/Al/Ni/Au metal scheme, therefore ohmic contacts with novel structures should be better candidates for high power and high frequency GaN devices.

关键词： Ohmic contacts Aluminum gallium nitride Gallium nitride Gold Nonhomogeneous media Contact resistance Electrical resistance measurement Surface morphology Surface resistance Thermal stability

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Low power Folding/Interpolating ADC with a novel dynamic encoder based on ROM theory

Low power Folding/Interpolating ADC with a novel dynamic enc...

引用

International Conference on Solid-State and Integrated Circuit Technology

作者： Jilei Yin Yuan Wang Song Jia Zhen Liu Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University China

ISBN: (纸本)9781424421855

A 6-bit 200 Msps Folding/Interpolating analog to digital converter (ADC) with a novel dynamic encoder based on Rom theory is presented. The Precharge & Evaluate dynamic circuit is employed in the novel encoder and the bit synchronization logic to achieve high speed and reduce power dissipation. Realized in SMIC 0.35 um digital CMOS process, the whole ADC consumes only 35 mW at a 3.3 V voltage supply.

关键词： Read only memory Voltage Logic circuits Power dissipation Logic arrays microelectronics Analog-digital conversion Signal generators Binary codes Tail

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A low power ROIC design for 1024×1024 IRFPA 9th

A low power ROIC design for 1024×1024 IRFPA

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International Conference on Solid-State and Integrated Circuit Technology

作者： Chang Liu Wengao Lu Zhongjian Chen Jing Li Yacong Zhang Lijiu Ji Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University China

ISBN: (纸本)9781424421855

A low power Read-Out Integrated Circuit (ROIC) for a short-wave Infra-Red Focal Plane Array (IRFPA) is designed as a prototype for 1024×1024 image system. Ripple integration and readout scheme as well as highly efficient power management is introduced to this design in order to decrease total power dissipation. To overcome the charge sharing problem caused by this low power readout scheme, novel low input capacitance column amplifier is proposed. The Data rate is about 10 M/s per channel, with a total power dissipation of 56 mW.

关键词： Power dissipation Capacitors Switches Linearity Detectors microelectronics Prototypes Parasitic capacitance MOSFET circuits Cooling

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The implementation methods of high speed FIR filter on FPGA

The implementation methods of high speed FIR filter on FPGA

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International Conference on Solid-State and Integrated Circuit Technology

作者： Ying Li Chungan Peng Dunshan Yu Xing Zhang Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University China

ISBN: (纸本)9781424421855

This paper implements a sixteen-order high-speed Finite Impose Response (FIR) filter with four different popular methods: Conventional multiplications and additions; Full custom Distributed Arithmetic (DA) scheme; Add-and-Shift method with advanced calculation schedule. Each scheme is analyzed in detail including implementing process and advantages and/or drawbacks in order to present a practical reference. All of these implementations are aimed to implement on Xilinx Spartan 3 devices and we also compare our results with an industry result produced by Xilinx CoregenTM also using Distributed Arithmetic. The premium add-and-shift method observes up to 80% reduction in total occupied slices and 63.3% versus the largest conventional parallel multiplication implementation.

关键词： Finite impulse response filter Field programmable gate arrays Arithmetic Job shop scheduling Digital signal processing microelectronics Energy consumption Programmable logic arrays Circuit synthesis Table lookup

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CMOS folding and interpolating ADC with a mixed-averaging distributed T/H circuit

CMOS folding and interpolating ADC with a mixed-averaging di...

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International Conference on Solid-State and Integrated Circuit Technology

作者： Zhen Liu Song Jia Yuan Wang Lijiu Ji Xing Zhang Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University China

ISBN: (纸本)9781424421855

An 8-bit 200 MHz low-power CMOS folding and interpolating analog-to-digital converter is presented. A novel mixed-averaging distributed T/H circuit is proposed to decrease the nonlinearity error of the ADC. The DNL/INL is 0.3/0.2 LSB according to MATLAB simulation results. This ADC is implemented in 0.5 um CMOS technology and the total power dissipation is merely 96 mW at a sampling rate of 200 MHz.

关键词： Sampling methods Power dissipation Switches Circuit simulation CMOS technology Synchronization Interpolation Clocks CMOS analog integrated circuits microelectronics

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A comprehensive study on Schottky barrier nanowire transistors (SB-NWTs): Principle, physical limits and parameter fluctuations

A comprehensive study on Schottky barrier nanowire transisto...

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International Conference on Solid-State and Integrated Circuit Technology

作者： Liangliang Zhang Zhaoyi Kang Runsheng Wang Ru Huang Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University China

ISBN: (纸本)9781424421855;9781424421862

P-type Schottky barrier nanowire transistors (p-SB-NWTs) are computational studied in this paper. We analyzed the working principle and physical limits on their performance in details. The impact of Schottky contact of SB-NWTs on the current drivability, gate control and RF performance are studied comparing with conventional silicon nanowire transistors (SNWTs). It is pointed out that the inferior performance of SB-NWTs can not be solved by changing the S/D or channel materials. On the other hand, small V t , F t and on-off ratio fluctuation caused by process variation on channel diameter are observed, which is an advantage of SB-NWTs.

关键词： Schottky barriers Fluctuations MOSFETs Silicon Tunneling Silicides Nanoscale devices microelectronics CMOS technology Contact resistance

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A novel linear histogram BIST for ADC

A novel linear histogram BIST for ADC

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International Conference on Solid-State and Integrated Circuit Technology

作者： Jianguo Ren Jianhua Feng Hongfei Ye Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University China

ISBN: (纸本)9781424421855

This paper proposes a novel histogram BIST scheme for ADC static testing. For a monotonic ADC, the out codes have an approximate stair-like proportional relationship to the input signal. Based on this property, a space decomposition technique is proposed to reduce the testing time. By utilizing this technique, ADC¿s static parameters can be estimated in shorter testing time with low hardware overhead. The availability of proposed histogram BIST scheme has been verified by simulation and the test results have been compared with those obtained from Verigy SOC 93000.

关键词： Histograms Built-in self-test Hardware microelectronics Laboratories Circuit testing Analytical models Parameter estimation Computational modeling Circuit faults

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A new configuration scheme for delay test in non-simple LUT FPGA designs

A new configuration scheme for delay test in non-simple LUT ...

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International Conference on Solid-State and Integrated Circuit Technology

作者： Botao Sun Jianhua Feng Teng Lin Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University China

ISBN: (纸本)9781424421855

With the increased use of FPGA in widespread applications, its¿ size and speed has been rapidly increased, so more and more problems associated with performance defects are emerging. Performance defects such as delay defects will not lead to a functional fault, but will limit the frequency of the system. Only Stuck-at testing has not been sufficient to guarantee the reliability and quality, so testing delay fault becomes necessary. In this paper, in order to improve the efficiency and coverage of delay test, we first select the most suitable delay fault model for FPGAs, which is a good simulation for the actual situation. At the same time we proposed a new configuration on the basis of this. This method takes full advantage of the FPGAs¿ reconfiguration feature. It not only omits complex test pattern generation, but also optimizes the BIST circuits to minimize the area cost, and reaches higher fault coverage. To verify the theory, we use Xilinx vertex4 devices on the experimental test, and achieved approving results.

关键词： Delay Testing Table lookup Field programmable gate arrays Circuit faults Frequency Circuit simulation Test pattern generators Built-in self-test Cost function

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Investigations on proton-irradiation-induced spacer damage in deep-submicron MOSFETs

Investigations on proton-irradiation-induced spacer damage i...

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International Conference on Solid-State and Integrated Circuit Technology

作者： Shoubin Xue Pengfei Wang Ru Huang Dake Wu Yunpeng Pei Wenhua Wang Xing Zhang Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University Beijing China

ISBN: (纸本)9781424421855;9781424421862

In this paper, we have focused our attention on DC characteristics degradation of 0.18 ¿m MOSFETs after 10-MeV proton irradiation. It is shown that the threshold voltage shift, the transconductance degradation and the saturation drain current decrease are lager in PMOSFETs, while small effects are exhibited in NMOSFETs. From the analysis, it is concluded that the basic damage mechanism is not ascribed to the gate oxide and the isolation. The origin of the observed changes is due to the damage in spacer oxides of the MOSFETs. The mechanism involved is that the energetic protons incident on the spacer region lose their energy to displace the atoms, give rise to many defects, and create a disordered region (displacement damage region), where many defects and traps can capture positive charges to make the static characteristics degraded. Therefore, it is pointed out that the sidewalls are one of sensitive regions for irradiation hardness.

关键词： MOSFETs Protons Degradation Voltage CMOS technology Dielectric breakdown microelectronics Space technology Laboratories circuits

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