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Recovery Characteristics of NBTI of pMOSFETs with Oxynitride Dielectrics Under Drain Bias

Recovery Characteristics of NBTI of pMOSFETs with Oxynitride...

引用

2008 9th International Conference on Solid-State and Integrated-Circuit Technology

作者： Jiaqi Yang Junyan Pan Lihua Huang Xiaoyan Liu Ruqi Han and Jinfeng Kang L.F.Zhang Z.W.Zhu C.C.Liao H.M.Wu Key Laboratory of Microelectronic Devices and Circuits Institute of MicroelectronicsPeking University Semiconductor Manufacturing International Corporation

In this paper,the recovery characteristics of negative bias temperature instability（NBTI） of pMOSFETs under drain bias were *** is observed that,the drain bias not only worsens the NBTI degradation in high |V| region but also suppresses the recovery ratio of *** time evolutions of recovery show that the drain bias dependent NBTI recovery is mainly related to the fast recovery effect in initial ls. While in long time scale,the recovery obeys power law dependence on time.A physical model based on donor-type interface traps neutralization at the beginning of recovery is proposed to explain the suppressed recovery ratio under drain bias.

关键词： Recovery Characteristics of NBTI of pMOSFETs with Oxynitride Dielectrics Under Drain Bias

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An Acquisition Circuit in Global Positioning System Receivers

An Acquisition Circuit in Global Positioning System Receiver...

引用

2008 9th International Conference on Solid-State and Integrated-Circuit Technology

作者： Xiaoxin Cui Chungan Peng Key Laboratory of Microelectronic Devices and Circuits Institute of MicroelectronicsPeking University Institute of Beijing Remote Sensing Information

The conventional matched filter structures are investigated in this paper,An acquisition circuit based on the polyphase form matched filter in Global Positioning System(GPS) receiver is *** the cost of less hardware resource,the significant advantage in the speed of synchronization is *** 32×128 polyphase form matched filter,the critical path delay approximately reduces 1/2,the sample frequency would be double.

关键词： An Acquisition Circuit in Global Positioning System Receivers

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Simulation of Charge Trapping Memory with Novel Structures

Simulation of Charge Trapping Memory with Novel Structures

引用

2008 9th International Conference on Solid-State and Integrated-Circuit Technology

作者： X.Y.Liu Y.C.Song Gang Du R.Q Han Z.L.Xia D.Kim K-H Lee Key Laboratory of Microelectronic Devices and Circuits Institute of MicroelectronicsPeking University Samsung Electronics Co.Ltd

＜正＞Ⅰ.Introduction Flash memories are one of the basic building blocks of today’s electronic *** floating gate type of Flash memory is impossible to scale down to beyond 45nm due to the difficulty in scaling the tunnel oxide and the gate coupling ratio[1].Because of the difficulty in maintaining high gate coupling ratio and preventing cross talk between neighboring cells,NAND technology is forecasted to migrate gradually from floating gate devices（FG） to charge trapping memory（CTM）[2]. CTM are not sensitive to tunnel oxide damage since the charge is stored in discrete traps and one weak spot does

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3-D Simulation of Geometrical Variations Impact on Nanoscale FinFETs

3-D Simulation of Geometrical Variations Impact on Nanoscale...

引用

2008 9th International Conference on Solid-State and Integrated-Circuit Technology

作者： Shimeng Yu Yuning Zhao Yuncheng Song Gang Du Jinfeng Kang Ruqi Han Xiaoyan Liu Key Laboratory of Microelectronic Devices and Circuits Institute of MicroelectronicsPeking University Shenzhen Graduate School Peking University

Intra-die fluctuations in the nanoscale CMOS technology emerge inherently to geometrical variations such as line edge roughness(LER) and oxide thickness fluctuations (OTF).A full 3-D statistical simulation is presented to investigate the impact of geometrical variations on the FinFETs *** this work,roughness is introduced by a Fourier analysis of the power spectrum of Gaussian autocorrelation *** influence of different geometrical variation sources is compared and *** results shows that FinFETs performance is most sensitive to the fin LER,which causes a remarkable shift and fluctuations in threshold voltage, drain induced barrier lower effect(DIBL) and leakage current. The impact of gate LER follows that of fin *** simulation also suggests quantum confinement effect accounts for the aggressive fluctuations due to fin LER.

关键词： D Simulation of Geometrical Variations Impact on Nanoscale FinFETs

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A New Method to Evaluate the Total Dose Radiation Effect of MOS devices

A New Method to Evaluate the Total Dose Radiation Effect of ...

引用

2008 9th International Conference on Solid-State and Integrated-Circuit Technology

作者： Hao Tang Yi Wang Jinyan Wang Yijun Zheng Yufeng Jin Key Laboratory of Microelectronic Devices and Circuits Institute of MicroelectronicsPeking University Peking University Shenzhen Graduate School

The total dose radiation effect（TDRE） has been regarded as one of the most harmful factors to degrade MOS *** this paper,a simple new method called avalanche injection of holes is introduced to simulate or displace the radiation experiments to determine the TDRE of MOS *** TDRE, avalanche injection of holes can also provide sufficient holes to flow into the gate oxide layer where a small part of these holes can be trapped in the defects and cause a shift of flat-band voltage(ΔV) of MOS device,we can conclude that the structure which has a greaterΔV would be easier to be affected by TDRE.

关键词： LPCVD A New Method to Evaluate the Total Dose Radiation Effect of MOS devices

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Impact of stochastic mismatch on FinFETs SRAM cell induced by process variation

Impact of stochastic mismatch on FinFETs SRAM cell induced b...

引用

IEEE Conference on Electron devices and Solid-State circuits

作者： Shimeng Yu Yuning Zhao Gang Du Jinfeng Kang Ruqi Han Xiaoyan Liu Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University China Shenzhen Graduate School Peking University

3-D mixed-mode device-circuit simulation is presented to investigate stochastic mismatch of FinFETs SRAM cell induced by process variation including fin-thickness and gate length variation as well as fin line edge roughness (LER). In this work, 20 nm FinFETs SRAMpsilas sensitivity of read and write static noise margin (SNM) to process variation is evaluated. The worst cases of read and write SNM under the influence of process variation are summarized. The results show that FinFETs SRAMpsilas stability is most sensitive to the access transistorpsilas fin-thickness variation. Under the worst cases, increasing the pull-down transistorpsilas fin-number may improve read SNM. The fin LER can cause aggressive fluctuations of the butterfly-curves and impose a big challenge on robust FinFETs SRAM design. Adopting 8T cell instead of 6T cell can alleviate the fin LER effect on read stability.

关键词： Stochastic processes FinFETs Random access memory MOSFETs Stability Fluctuations CMOS technology Stochastic resonance MOS devices Robustness

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Theoretical study of low-energy electron penetration in resist-substrate target by Monte Carlo simulation

Theoretical study of low-energy electron penetration in resi...

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International Conference on Solid-State and Integrated Circuit Technology

作者： Liming Ren Baoqin Chen Ru Huang Xing Zhang Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University Beijing China Chinese Academy and Sciences Beijing China

ISBN: (纸本)9781424421855

Low-energy electron beam lithography has a variety of advantages. The traditional electron scattering model consisting of Rutherford elastic scattering cross section and Bethe continuous slowing down approximation formula are not suitable for low-energy electron beam lithography. A more accurate physical model describing the low-energy electron scattering processes was proposed in this work. And Monte Carlo method was used to simulate the complex scattering processes of Gaussian-distribution low-energy electron beam in the target of thin film on thick substrate. The simulation results show that low-energy electron beam lithography has advantages of high throughput, low proximity effects and small damage to the underlying substrate. It is in agreement with the conclusion got from Lee et al¿s and Peterson et al¿s experiments.

关键词： Particle scattering Electron beams Lithography Substrates microelectronics Gaussian processes Throughput Proximity effect Energy resolution Polynomials

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New method to evaluate the total dose radiation effect of MOS devices

New method to evaluate the total dose radiation effect of MO...

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International Conference on Solid-State and Integrated Circuit Technology

作者： Hao Tang Yi Wang Jinyan Wang Yijun Zheng Yufeng Jin Peking University Beijing Beijing CN Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University Beijing China

ISBN: (纸本)9781424421855

The total dose radiation effect (TDRE) has been regarded as one of the most harmful factors to degrade MOS devices. In this paper, a simple new method called avalanche injection of holes is introduced to simulate or displace the radiation experiments to determine the TDRE of MOS devices. Like TDRE, avalanche injection of holes can also provide sufficient holes to flow into the gate oxide layer where a small part of these holes can be trapped in the defects and cause a shift of flat-band voltage (¿V FB ) of MOS device, we can conclude that the structure which has a greater ¿V FB would be easier to be affected by TDRE.

关键词： Radiation effects MOS devices Voltage microelectronics Electron traps Electrodes Frequency Laboratories circuits Degradation

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A low-voltage voltage doubler without body effect

A low-voltage voltage doubler without body effect

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International Conference on Solid-State and Integrated Circuit Technology

作者： Ming Li Li-Wu Yang Jinfeng Kang Yangyuan Wang Semiconductor Manufacturing International Corporation Shanghai China Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University China

ISBN: (纸本)9781424421855

A voltage doubler, which avoids body effect and then improves rise time and efficiency even with 1 V power supply, is presented. This art is designed for word line boosting, using 0.18 um EEPROM technology. Not only the voltage doubler can work with capacitive load normally, but also it can supply load current and achieve higher efficiency. The whole circuit can be implemented on chip and is suitable for low voltage application. In addition, theoretical analysis and simulation results have been given.

关键词： Power supplies MOSFETs Threshold voltage Boosting EPROM Low voltage Charge pumps microelectronics Circuit simulation Switches

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Simulation of charge trapping memory with novel structures

Simulation of charge trapping memory with novel structures

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International Conference on Solid-State and Integrated Circuit Technology

作者： X. Y. Liu Y. C. Song Gang Du R.Q. Han Z. L. Xia D. Kim K.-H. Lee Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University Beijing China Samsung Electronics Company Limited South Korea

The floating gate type of flash memory is impossible to scale down to beyond 45 nm due to the difficulty in scaling the tunnel oxide and the gate coupling ratio. Because of the difficulty in maintaining high gate coupling ratio and preventing cross talk between neighboring cells, NAND technology is forecasted to migrate gradually from floating gate devices (FG) to charge trapping memory (CTM). CTM are not sensitive to tunnel oxide damage since the charge is stored in discrete traps and one weak spot does not cause all stored charge to leak out as in floating gate devices. The NAND HC-TANOS flash cell has been generated in three dimensional TCAD tools with 38 nm gate length, 34 nm channel width and charge trapping structures. A structure of Al 2 O 3 (15 nm)/Si 3 Na (6.5 nm)/SiO 2 (4.5 nm) with TaN gate was employed as the gate stack. To study the effects of gate stack coverage on flash cell's performance, the shape of gate stack is varied while keeping all other structural parameters fixed.

关键词： Tunneling Shape Circuit simulation Electron traps Nonvolatile memory microelectronics Flash memory Poisson equations Failure analysis Laboratories

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