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Generation of single-focus phase singularity by the annulusquadrangle-element coded binary square spiral zone plates

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Science China(Physics,Mechanics & Astronomy) 2022年第9期65卷 72-78页

作者： Huaping Zang Zhuanglei Miao Mengguang Wang Quanping Fan Lai Wei Chuanke Wang Weimin Zhou Yilei Hua Leifeng Cao Xinlian Xue Haizhong Guo Key Laboratory of Material Physics Ministry of EducationSchool of Physics and MicroelectronicsZhengzhou UniversityZhengzhou 450052China Science and Technology on Plasma Physics Laboratory Laser Fusion Research CenterChina Academy of Engineering PhysicsMianyang 621900China Laboratory of Microelectronic Devices and Integrated Technology Institute of MicroelectronicsChinese Academy of SciencesBeijing 100029China School of Engineering Physics Shenzhen Technology UniversityShenzhen 518118China Collaborative Innovation Center of Light Manipulations and Applications Shandong Normal UniversityJinan 250358China

Optical vortices(OVs) with unique square symmetry are widely used in various applications including particle manipulation,microscopy, and image processing. However, the undesired higher-order foci introduced by the conventional vortex lens such as square spiral zone plates(SSZPs) may lead to additional artifacts and thus degrade contrast sensitivity. In this endeavor, herein,we propose a methodology to combine the merit of SSZPs and the advantage of Gabor zone plates(GZPs) in establishing a specific single optical element, termed binary single focused square spiral zone plates(BSSZPs). In contrast to the abrupt transitions of the SSZPs, our central idea aims to realize the sinusoidal transmittance along the radial direction of SSZPs by a series of randomly distributed annulus-quadrangle-shaped nanometer structure apertures. The innovative design can simultaneously generate OVs with unique square symmetry, and eliminate the interference of higher-order foci along the propagation direction. Guided by our theoretical predication, the focusing property of such optics was further experimentally *** findings are expected to direct new avenue towards improving the performance of optical image processing and alignment system.

关键词： optical vortices higher-order diffraction spiral zone plates topological charges

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An Area-Efficient Deblocking Filter Architecture for Multi-standard Video Codec 4

An Area-Efficient Deblocking Filter Architecture for Multi-s...

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4th IEEE International Conference on circuits and Systems, ICCS 2022

作者： Li, Sirui Huang, Leilei Xiong, Xiankui Xu, Dong Zhu, Xuanpeng Fan, Yibo Fudan University School of Microelectronics Shanghai China Institute of Microelectronic Circuits and Systems East China Normal University Shanghai China State Key Laboratory of Mobile Network Mobile Multimedia Technology Zte Corporation Shenzhen China

ISBN: (数字)9781665460361

ISBN: (纸本)9781665460361

Video needs to be compressed before transmission or storage, and the continuous development of video coding standards has brought about the need for multi-standard video codecs. Deblocking filter is an important tool to improve the efficiency of video coding in both the H.264 Advanced Video Coding (H.264/AVC) standard and the High Efficiency Video Coding (HEVC) standard. To support these two standards, this paper proposes an area-efficient general deblocking filter hardware architecture. The proposed architecture reuses similar parts in the filter to control the increased area cost of supporting multiple standards and achieves a 37% gate count reduction. And by switching the connection form of filter modules between series and parallel, a good trade-off is made between throughput and area. The architecture has a throughput of 8K@60fps in H.264/AVC and 8K@160fps in HEVC. The experimental result shows that the multi-standard architecture consumes 61.3k gates at 526 MHz in GF 28 nm process, and the design has been successfully integrated into a multi-standard video codec. © 2022 IEEE.

关键词： Image coding

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Memory materials and devices:From concept to application

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InfoMat 2020年第2期2卷 261-290页

作者： Zhenhan Zhang Zongwei Wang Tuo Shi Chong Bi Feng Rao Yimao Cai Qi Liu Huaqiang Wu Peng Zhou State Key Laboratory of ASIC and System School of MicroelectronicsFudan UniversityShanghaiChina Key Laboratory of Microelectronic Devices and Circuits(MOE) Institute of MicroelectronicsPeking UniversityBeijingChina Key Laboratory of Microelectronic Devices and Integrated Technology Institute of MicroelectronicsChinese Academy of SciencesBeijingChina College of Materials Science and Engineering Shenzhen UniversityShenzhenChina Institute of Microelectronics Tsinghua UniversityBeijingChina

Memory cells have always been an important element of information *** emerging technologies like big data and cloud computing,the scale and complexity of data storage has reached an unprecedented peak with a much higher requirement for memory *** is well known,better data storage is mostly achieved by ***,as the size of the memory device is reduced,a series of problems,such as drain gate-induced leakage,greatly hinder the performance of memory *** meet the increasing demands of information technology,novel and high-performance memory is urgently ***,emerging memory technologies are expected to improve memory performance and drive the information *** review will focus on the progress of several emerging memory technologies,including two-dimensional material-based memories,resistance random access memory(RRAM),magnetic random access memory(MRAM),and phasechange random access memory(PCRAM).Advantages,mechanisms,and applications of these diverse memory technologies will be discussed in this review.

关键词： memory MRAM PCRAM RRAM two-dimensional material

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Deep insight into the voltage amplification effect from ferroelectric negative capacitance

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Science China(Information Sciences) 2019年第8期62卷 216-218页

作者： Huimin WANG Qianqian HUANG Mengxuan YANG Xing ZHANG Ru HUANG Key Laboratory of Microelectronic Devices and Circuits (MOE) Institute of Microelectronics

Dear editor,Power dissipation has become one of the most serious problems for nano-electronics. For conventional transistors, the operation voltage cannot be continuously reduced due to the fundamental limitation of subthreshold swing (SS)(60 mV/decade at room temperature)[1, 2]. The voltage amplification (VA) induced by the negative capacitance

关键词： Deep insight into the voltage amplification effect from ferroelectric negative capacitance

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Rectangular suspended single crystal Si nanowire with (001) planes and direction developed via TMAH wet chemical etching

Rectangular suspended single crystal Si nanowire with (001) ...

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2020 China Semiconductor Technology International Conference, CSTIC 2020

作者： Sun, Shuang Zhang, Baotong Yang, Yuancheng An, Xia Xu, Xiaoyan Huang, Ru Li, Ming Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University Beijing100871 China

ISBN: (纸本)9781728165585

In this study, a kind of rectangular suspended single crystal Si nanowire with (001) planes and along direction is developed via a CMOS-compatible top-down scheme. In this scheme, the nanowires are formed by anisotropic etching of TMAH on different silicon crystallography orientations. By designing the initial orientations of hard mask patterns, the rectangular suspended silicon nanowires can be successfully fabricated without any sacrificial epitaxial layers. Due to the damage-free process and the high mobility on (001) planes, this scheme will provide a high-quality channel for the future gate-alI-around silicon transistor technology. © 2020 IEEE.

关键词： Nanowires

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Redox Memristors with Volatile Threshold Switching Behavior for Neuromorphic Computing

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Journal of Electronic Science and Technology 2022年第4期20卷 356-374页

作者： Yu-Hao Wang Tian-Cheng Gong Ya-Xin Ding Yang Li Wei Wang Zi-Ang Chen Nan Du Erika Covi Matteo Farronato Dniele Ielmini Xu-Meng Zhang Qing Luo Key Laboratory of Microelectronic Devices and Integrated Technology Institute of Microelectronics of the Chinese Academy of SciencesBeijing 100029 University of Chinese Academy of Sciences Beijing 100049 Peng Cheng Laboratory Shenzhen 518055 Institute for Solid State Physics University of JenaJena 07743 Department of Quantum Detection Leibniz Institute of Photonic TechnologyJena 07743 Nanoelectronic Materials Laboratory Dresden 01187 Department of Electronics Information and BioengineeringPolitecnico di MilanoMilan 20133 Frontier Institute of Chip and System Fudan UniversityShanghai 200433

The spiking neural network(SNN),closely inspired by the human brain,is one of the most powerful platforms to enable highly efficient,low cost,and robust neuromorphic computations in hardware using traditional or emerging electron devices within an integrated *** the hardware implementation,the building of artificial spiking neurons is fundamental for constructing the whole ***,with the slowing down of Moore’s Law,the traditional complementary metal-oxide-semiconductor(CMOS)technology is gradually fading and is unable to meet the growing needs of neuromorphic ***,the existing artificial neuron circuits are complex owing to the limited bio-plausibility of CMOS *** with volatile threshold switching(TS)behaviors and rich dynamics are promising candidates to emulate the biological spiking neurons beyond the CMOS technology and build high-efficient neuromorphic ***,the state-of-the-art about the fundamental knowledge of SNNs is ***,we review the implementation of TS memristor-based neurons and their systems,and point out the challenges that should be further considered from devices to circuits in the system *** hope that this review could provide clues and be helpful for the future development of neuromorphic computing with memristors.

关键词： Memristors neuromorphic computing threshold switching

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Impact of Time Delay Schemes on Reliability Degradation during Program/Erase Cycling in HZO-based FeFETs

Impact of Time Delay Schemes on Reliability Degradation duri...

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IEEE Silicon Nanoelectronics Workshop (SNW)

作者： Xiaopeng Li Guoqing Zhao Lu Tai Pengpeng Sang Xiaoyu Dou Xuepeng Zhan Xiaolei Wang Jixuan Wu Jiezhi Chen School of Information Science and Engineering (ISE) Shandong University Qingdao China Key Laboratory of Microelectronic Devices and Integrated Technology Institute of Microelectronics of Chinese Academy of Sciences Beijing China

ISBN: (数字)9798350391633

ISBN: (纸本)9798350391640

The commercialization of HZO-based FeFETs is hindered by issues such as MW degradation and poor endurance. In this study, we systematically investigate degradation suppression using time delay schemes. Our findings reveal that symmetric time delay during cycling fails to effectively mitigate MW and SS degradation. Interestingly, we observe that the optimization of MW or SS can be achieved through asymmetric delay (i.e., time delay only after program or erase). It’s found that delay after programming (P-delay) effectively suppresses MW degradation, while delay after erasure (E-delay) proves effective in mitigating SS degradation. This study offers valuable insights into the reliability optimization of HZO-based FeFETs.

关键词： Degradation Delay effects Conferences Programming Silicon Delays Reliability

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A photomemory by selective-assembling hybrid porphyrin-silicon nanowire field-effect transistor

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Science China(Information Sciences) 2020年第6期63卷 253-255页

作者： Gong CHEN Bocheng YU Xiaokang LI Xiaoqiao DONG Xiaoyan XU Zhihong LI Ru HUANG Ming LI Key Laboratory of Microelectronic Devices and Circuits(MOE) Institute of MicroelectronicsPeking University National Key Laboratory of Science and Technology on Micro/Nano Fabrication Peking University Faculty of Information Technology Beijing University of Technology

Dear editor,Recently, the integration of photosensitive material and electronic nanodevice has been the center of attention with Internet of things (IoT)technology development [1–3]. The immobilization of such photoactive molecules on the semiconductor surface was necessarily adopted to employ their photoelectric characteristics which can be observed in the solution. Porphyrin-based hybrid transistors have emerged as promising candidates for photonic sensing application due to the

关键词： A photomemory by selective-assembling hybrid porphyrin-silicon nanowire field-effect transistor

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A High Dynamic Range Pixel Circuit with High-voltage Protection for 128×128 Linear-mode APD Array 15

A High Dynamic Range Pixel Circuit with High-voltage Protect...

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15th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2020

作者： Gu, Yuting Lu, Wengao Niu, Yuze Zhang, Yacong Chen, Zhongjian Key Laboratory of Microelectronic Devices and Circuits Peking University Department of Microelectronics China

ISBN: (纸本)9781728162355

This paper presents a high dynamic range pixel circuit with high-voltage protection for 128×128 Linear-mode avalanche photodiode (LM-APD) array. The pixel circuit includes a high-voltage transistor, a pixel-level analog-to-digital converter (ADC), and a high-voltage protection circuit based on circuit-shared. Through circuit-shared, the pixel-level A/D conversion and high-voltage protection are completed efficiently. Meanwhile, the dynamic range of the entire circuit is greatly improved. The chip is designed in 0.18µm CMOS process. The frame rate is 100Hz and the resolution is 16bit. The simulation results indicate that the dynamic range is 94dB and the power consumption is 5µW per pixel. The pixel pitch is 100µm, which can be reduced further with smaller APD detector. © 2020 IEEE.

关键词： Surge protection

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Modeling Non-Uniformity During Two-Step Dry Etching of Si/SiGe Stacks for Gate-All-Around FETs

Modeling Non-Uniformity During Two-Step Dry Etching of Si/Si...

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International Conference on Simulation of Semiconductor Processes and devices (SISPAD)

作者： Ziyi Hu Lado Filipovic Junjie Li Lingfei Wang Zhicheng Wu Rui Chen Yayi Wei Ling Li State Key Laboratory of Fabrication Technologies for Integrated Circuits Institute of Microelectronics Chinese Academy of Sciences Beijing China CDL for Multi-Scale Process Modeling of Semiconductor Devices and Sensors Institute for Microelectronics TU Wien Vienna Austria

ISBN: (数字)9798331516352

ISBN: (纸本)9798331516369

Selective lateral etching of the SiGe layers is one of the most critical steps in Gate-All-Around Field-Effect Transistor (GAAFET) fabrication, which is the basis for the formation of an inner-spacer. Non-uniformity of substrate surface during wet or dry selective etching of SiGe is a common sight in industry, which cannot be modeled using standard process Technology Computer Aided Design (TCAD) approaches. In this paper, we propose a method for the continuous simulation of the two-step dry etching process - anisotropic etching of the Si/SiGe stack and subsequent isotropic selective etching of SiGe - to study the mechanism behind the non-uniform profile formation. The proposed method is able to simulate the non-uniform profile accurately, which was calibrated and verified with experimental data.

关键词： Industries Fabrication Design automation Dry etching Field effect transistors Logic gates Semiconductor process modeling Substrates Standards Silicon germanium

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