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10th IEEE International Power Electronics and Motion Control Conference, IPEMC 2024 ECCE Asia

作者： Jia, Daoyong Jiang, Xi Wang, Ying Ma, Nianlong Ouyang, Renze Yuan, Song Gong, Xiaowu Xidian University The Key Laboratory of Ministry of Education for Wide Bandgap Semiconductor Materials and Devices School of Microelectronics Xi'an710071 China Xidian University Guangzhou Institute of Technology Guangzhou510555 China Shenzhen Smartchip Microelectronics Technology Company Ltd. Shenzhen518000 China

ISBN: (纸本)9798350351330

Parasitic inductance reduction in the SiC power module is a crucial aspect in power module design, which can help to decrease energy losses and improve the module's efficiency. This paper proposes an innovative layout for 1200V SiC MOSFET half-bridge power module to lower the parasitic inductance within the power loop and the thermal resistance. Through an extensive evaluation of how upper and lower bridge chip distances affect parasitic inductance and thermal resistance, an optimal chip spacing is selected. Following double pulse experimental test, the fabricated module is benchmarked against a same current rating commercial 1200V SiC MOSFET half-bridge module, exhibits superior switching performance. © 2024 IEEE.

关键词： Silicon carbide

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Recent progress on fabrication and flat-band physics in 2D transition metal dichalcogenides moiré superlattices

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Journal of Semiconductors 2023年第1期44卷 43-55页

作者： Xinyu Huang Xu Han Yunyun Dai Xiaolong Xu Jiahao Yan Mengting Huang Pengfei Ding Decheng Zhang Hui Chen Vijay Laxmi Xu Wu Liwei Liu Yeliang Wang Yang Xu Yuan Huang Advanced Research Institute of Multidisciplinary Science Beijing Institute of TechnologyBeijing 100081China Beijing National Laboratory for Condensed Matter Physics Institute of PhysicsChinese Academy of SciencesBeijing 100190China School of Physical Sciences University of Chinese Academy of SciencesBeijing 100049China School of Integrated Circuits and Electronics MIIT Key Laboratory for Low-Dimensional Quantum Structure and DevicesBeijing Institute of TechnologyBeijing 100081China BIT Chongqing Institute of Microelectronics and Microsystems Chongqing 401332China

Moiré superlattices are formed when overlaying two materials with a slight mismatch in twist angle or lattice constant. They provide a novel platform for the study of strong electronic correlations and non-trivial band topology, where emergent phenomena such as correlated insulating states, unconventional superconductivity, and quantum anomalous Hall effect are discovered. In this review, we focus on the semiconducting transition metal dichalcogenides(TMDs) based moiré systems that host intriguing flat-band physics. We first review the exfoliation methods of two-dimensional materials and the fabrication technique of their moiré structures. Secondly, we overview the progress of the optically excited moiré excitons, which render the main discovery in the early experiments on TMD moiré systems. We then introduce the formation mechanism of flat bands and their potential in the quantum simulation of the Hubbard model with tunable doping, degeneracies, and correlation strength. Finally, we briefly discuss the challenges and future perspectives of this field.

关键词： flat-band physics two-dimensional materials moirésuperlattices Hubbard model moiréexcitons

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Complementary tunneling transistors based on WSe2/SnS2 van der Waals heterostructure

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Science China(Information Sciences) 2020年第4期63卷 245-247页

作者： Rundong JIA Liang CHEN Qianqian HUANG Ru HUANG Key Laboratory of Microelectronic Devices and Circuits (MOE) Institute of Microelectronics Peking University

Dear editor,Two-dimensional (2D) semiconductors have emerged as one of the most promising material candidates for next-generation electronic devices [1].Owing to the broad range of bandgap diversity and the pristine i... 详细信息

关键词： Complementary tunneling transistors based on WSe2/SnS2 van der Waals heterostructure VDS

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Influence of Interfacial Layers and High-k Post Dielectric Annealing On the Characteristics of MOS devices

Influence of Interfacial Layers and High-k Post Dielectric A...

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2023 China Semiconductor Technology International Conference, CSTIC 2023

作者： Sang, Guanqiao Zhang, Qingzhu Yin, Huaxiang Li, Junfeng Qin, Xulei Institute of Microelectronics of Chinese Academy of Sciences Key Laboratory of Microelectronics Devices and Integrated Technology Beijing100029 China University of Chinese Academy of Sciences Beijing100049 China ChangChun University of Science and Technology Changchun130022 China

ISBN: (纸本)9798350311006

In this paper, investigation of the effects of Post Dielectric Annealing (PDA) and Interfacial Layers (IL) on the characteristics of Metal-Oxide-Semiconductor (MOS) devices. Based on the traditional MOS fabrication process, the PDA method provides a solution to the problem of large interface trap density (Dit) after direct deposition of HfO2 medium, and successfully reduces Dit by about 78%. At the same time, compare the interface state and electrical characteristics of various IL layer deposition methods. The results showed that the Atomic Layer Deposition (ALD) method reduced Dit by nearly 60% over the thermal oxidation method. And the positive shift of the flat band voltage (Vfb) was increased by about 150 m. In addition, analyze the relationship between the change of Vfb and the internal charge of the dielectric layer is analyzed, it is found that annealing and IL layer dielectric deposition methods change Vfb by affecting the interface defect charge (Qit) and oxide defect charge (Qot). In this work, the results provide a guidance for the interface optimization of advanced devices. © 2023 IEEE.

关键词： MOS devices

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A multiphysics SET modeling method based on machine learning

A multiphysics SET modeling method based on machine learning

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作者： Xu, Ting Guo, Yanping Chen, Jiaxin Bu, Jianhui Gao, Libo Ni, Tao Li, Bo Institute of Microelectronics of the Chinese Academy of Sciences Beijing China Key Laboratory of Science and Technology on Silicon Devices Chinese Academy of Sciences Beijing China University of Chinese Academy of Sciences Beijing China

With continuous downscaling of transistor sizes, the sensitivity to single event effect (SET) has become one of the most important reliability issues for aerospace integrated circuits. Besides the SET, integrated circuits will be affected by multiphysics such as temperature and voltage when working in space. Currently, the commonly used modeling methods are based on physical mechanisms and the double exponential pulse current. However, both methods are hard to build an accurate SET current model when various variables are considered. In this article, a novel machine learning modeling method of multiphysics SET is proposed, using intelligent algorithms to optimize the network also. With this method, we can obtain a reasonable and accurate multiphysics SET model based on neural network with single hidden layer, and there is no need to consider complex physical mechanisms. The model data is collected from TCAD simulation. Ant colony algorithm was used to optimize the initial values of the network. The RMS (root mean square error) of modeling result is less than 2%. © 2024 John Wiley & Sons Ltd.

关键词： Multiphysics

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0.1V Low Power Bandgap Reference For RRAM Storage Applications 16

0.1V Low Power Bandgap Reference For RRAM Storage Applicatio...

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16th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2022

作者： Han, Yongkang Zhang, Wenjun Cao, Yue Jiang, Haijun Zhou, Ruixi Xu, Xiaoxin Yang, Jianguo Zhejiang Lab Hangzhou311121 China Institute of Microelectronics of the Chinese Academy of Sciences Key Laboratory of Microelectronics Devices and Integrated Technology Beijing100029 China

ISBN: (数字)9781665469067

ISBN: (纸本)9781665469067

This article proposes a bandgap for RRAM storage, which can work at a minimum of 0.7V power supply and provide a reference voltage of 0.1V. The circuit uses sub threshold technology to reduce the power supply voltage, symmetrical OTA structure to improve the PVT characteristics, and cascode technology to improve the accuracy of reference current. The temperature coefficient (TC) of 1.4ppm/°C was obtained under the 0.18um process from 0 to 100°C, and 1.5uA current was finally consumed under the 0.9V power supply voltage. © 2022 IEEE.

关键词： Energy gap

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High-performance sub-50nm channel length 3d monolithically stackable vertical igzo tfts for active-matrix application 59th

High-performance sub-50nm channel length 3d monolithically s...

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59th International Symposium, Seminar and Exhibition, Display Week 2022

作者： Duan, Xinlv Huang, Kailiang Feng, Junxiao Yin, Shihui Wang, Zhaogui Jiao, Guangfan Wu, Ying Jing, Weiliang Wang, Zhengbo Li, Jingyu Xu, Jeffrey Chen, Chuanke Chen, Qian Chuai, Xichen Lu, Congyan Yang, Guanhua Geng, Di Li, Ling Liu, Ming Key Laboratory of Microelectronics Devices and Integrated Technology Institute of Microelectronics of the Chinese Academy of Sciences Beijing China Huawei Technologies Co. LTD China

For the first time, we propose a stackable vertical Channel-All-Around (CAA) IGZO FETs. The device is fabricated in a BEOL-compatible process flow where the channel and gate stack is deposited by Plasma-Enhanced Atomic Layer Deposition (PEALD). The impact of IGZO cycle ratio and plasma power on the device electrical performance are studied. An optimized 50nm-channel-length CAA IGZO FET achieved Ion >30μA/μm and Ioff below 1.8×10-17μA/μm at VDS = 1V. © 2022. John Wiley and Sons Inc. AIAA. All rights reserved.

关键词： Thin film transistors

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Super retina TFT based full color microLED display via laser mass transfer

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Science China(Information Sciences) 2024年第11期67卷 5-19页

作者： Xu YANG Jinchai LI Xuhui PENG Chunfeng ZHAO Chao CHEN Xiaowei ZHANG Jinliang LIN Donghua LI Yuefen CHEN Zhaoxia BI Feng QIN Cheng LI Kai HUANG Junyong KANG Rong ZHANG Fujian Key Laboratory of Semiconductor Materials and Applications CI Center for OSEDEngineering Research Center of Micro-nano Optoelectronic Materials and Devices Ministry of EducationDepartment of Physics Xiamen University Future Display Institute of Xiamen Tianma Microelectronics Co. Ltd. School of Electronic Science and Engineering Xiamen University Tianma Advanced Display Technology Institute (Xiamen) Co. Ltd.

MicroLED display is considered one of the most promising technologies for next-generation displays. However, the high manufacturing cost has been a major obstacle to its accessibility to the general consumer market, and mass transfer, an essential process to achieve cost-effective manufacturing, has not yet reached commercial maturity. Critical issues, such as microLED chips, transfer equipments, and process materials, need to be addressed for the mass transfer technologies. In this work, we present a 1.63-inch full color microLED display module fabricated with laser mass transfer, which has a pixel density of 403 pixels per inch(PPI), the highest resolution ever achieved in the industry using mass transfer technologies. The laser mass transfer is realized with three process nodes: laser lift-off, laser induced forward transfer, and carrier bonding. Each node has been well explored to improve yields. Insights into the present progress and the future development of the laser mass transfer will be shared in this work.

关键词： microLED mass transfer LLO chip on wafer chip on carrier

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Investigation of Synergic Hydrogen Mitigation Technique for Top-Gate A-IGZO Thin-Film Transistors

Investigation of Synergic Hydrogen Mitigation Technique for ...

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2023 China Semiconductor Technology International Conference, CSTIC 2023

作者： Yan, Gangping Song, Zhiyu Xu, Haoqing Yang, Shangbo Niu, Chuqiao Tian, Guoliang Luo, Yanna Zhang, Luoyun Bao, Yunjiao Xu, Gaobo Yin, Huaxiang Key Laboratory of Microelectronics Devices and Integrated Technology Institute of Microelectronics of Chinese Academy of Sciences Beijing100029 China University of Chinese Academy of Sciences Beijing100049 China Beijing Superstring Academy of Memory Technology Beijing100176 China

ISBN: (纸本)9798350311006

In this work, a simple hydrogen mitigation method for the top-gate amorphous In-Ga-Zn-O thin-film transistor (a-IGZO TFT) is proposed. The influences of synergic modulations between post-dielectric thermal treatment and Al2O3 buffer layer acting as oxygen-blockers are investigated to address hydrogen issues. Using the proposed optimization approach, the self-aligned channel annealing is successfully performed to realize >104x increase in on-current of a-IGZO TFTs. These results provide useful guidance for high-performance a-IGZO devices in monolithic three-dimensional integration. © 2023 IEEE.

关键词： Thin film transistors

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Enhancement of fMAX of InP-based HEMTs by double-recessed offset gate process

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Chinese Physics B 2022年第5期31卷 743-748页

作者： Bo Wang Peng Ding Rui-Ze Feng Shu-Rui Cao Hao-Miao Wei Tong Liu Xiao-Yu Liu Hai-Ou Li Zhi Jin Guangxi Key Laboratory of Precision Navigation Technology and Application Guilin University of Electronic TechnologyGuilin 541004China High-Frequency High-Voltage Device and Integrated Circuits Center Institute of MicroelectronicsChinese Academy of SciencesBeijing 100029China

A double-recessed offset gate process technology for In P-based high electron mobility transistors(HEMTs)has been developed in this ***-recessed and double-recessed HEMTs with different gate offsets have been fabricated and *** with single-recessed devices,the maximum drain-source current(I_(D,max))and maximum extrinsic transconductance(g_(m,max))of double-recessed devices decreased due to the increase in series ***,in terms of RF performance,double-recessed HEMTs achieved higher maximum oscillation frequency(f_(MAX))by reducing drain output conductance(g_(m,max))and drain to gate capacitance(C_gd).In addition,further improvement of fMAXwas observed by adjusting the gate offset of double-recessed *** can be explained by suppressing the ratio of C_(gd)to source to gate capacitance(C_gd)by extending drain-side recess length(Lrd).Compared with the single-recessed HEMTs,the f;of double-recessed offset gate HEMTs was increased by about 20%.

关键词： InP HEMT maximum oscillation frequency(fMAX) double-recess offset gate

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