The number of the dummy via can significantly affect the interconnect average *** paper explores the modeling of the interconnect average temperature in the presence of multiple dummy *** proposed model incorporates t...
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The number of the dummy via can significantly affect the interconnect average *** paper explores the modeling of the interconnect average temperature in the presence of multiple dummy *** proposed model incorporates the multi-via effect into the effective thermal conductivity of the interlayer dielectric (ILD) to obtain accurate *** different ILDs,the multi-via effect is analyzed and ***,the extended applications of the multi-via effect are presented in this paper to obtain the minimum interconnect average temperature increase with a given via separation or *** study suggests that the multi-via effect should be accounted for in integrated circuits design to optimize the performance and design accuracy of integrated circuits.
A detail experimental study on the reliability degradation of pMOSFET under non-uniform NBTI stress was conducted. The relationship of drain bias under non-uniform NBTI stress was obtained and a turning curve was foun...
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A detail experimental study on the reliability degradation of pMOSFET under non-uniform NBTI stress was conducted. The relationship of drain bias under non-uniform NBTI stress was obtained and a turning curve was found. The non-uniform stress induced degradation can be separated into two different region based on the drain bias dependency, and the model for each region was developed and evaluated under various voltage and temperature. In addition, the conventional and enhanced NBTI stress demonstrated reverse temperature dependency. The non-uniform NBTI stress exhibited much lower recovery level, and its acceleration factor was similar to pure NBTI stress. From the temperature and voltage acceleration point of view, our results show that the non-uniform NBTI stress becomes the worst reliability corner for pMOSFETs with ultra thin gate oxynitride. The NBTI degradation with nominal drain bias was proposed to become as a device lifetime monitor for pMOSFETs.
RapidIO is a high performance open standard for the next-generation embedded interconnection technology. In this paper, an improved pivotal buffer core which plays a crucial role in the RapidIO packet transmission is ...
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RapidIO is a high performance open standard for the next-generation embedded interconnection technology. In this paper, an improved pivotal buffer core which plays a crucial role in the RapidIO packet transmission is described in detail. It uses the four-isolated-queue as the outbound framework for better quality of service and a certain amount of blocks with sharing and binding attempts mechanism as the main inbound structure for higher space utilization. It supports the advanced transmitter-controlled flow control so as to effectively manage the buffer space. Simulation results show that the valid link data utilizations of the proposed design with transmitter-controlled flow control could be kept over 95%, comparing to the fact that those of the buffers with basic receiver-controlled flow control gradually decrease to lower than 50% in the same condition.
For the silicided GGn MOS as ESD protection device, the current localization in the n+ diffusion duo to the short contact spacing often degrades the ESD performance of the device. By enlarging the contact spacing, bal...
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For the silicided GGn MOS as ESD protection device, the current localization in the n+ diffusion duo to the short contact spacing often degrades the ESD performance of the device. By enlarging the contact spacing, ballasting resistance is introduced to allow a more uniform current distribution. How the drain contact to gate spacing and contact to contact spacing influencing the ESD performance of the GGn MOS is investigated. We find that lengthening the contact to contact spacing can significantly improve the ESD performance of silicided GGn MOS.
A novel on-chip CMOS current sensor implemented by switched capacitors for a current - mode buck converter is presented in this paper. This proposed current sensing circuit does not need another sense MOSFET and a vol...
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A novel on-chip CMOS current sensor implemented by switched capacitors for a current - mode buck converter is presented in this paper. This proposed current sensing circuit does not need another sense MOSFET and a voltage-to-current and current-to-voltage transform circuit. We use the 0.35um DPTM CMOS process to design and simulate this circuit. Test result shows that the accuracy and the speed of the proposed current sensing circuit are high.
A low power high speed Readout Integrated Circuit(ROIC) design for 320 × 320 IRFPA is proposed in this paper. The ROIC operates as follows: after integration phase, voltages on column bus of odd rows and even row...
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A low power high speed Readout Integrated Circuit(ROIC) design for 320 × 320 IRFPA is proposed in this paper. The ROIC operates as follows: after integration phase, voltages on column bus of odd rows and even rows are read out alternately. And the results are sampled and stored alternately on two sample capacitors added at the output point of column CSA. When sample capacitor for odd row samples and holds data, sample capacitor for even row works as feedback capacitor of output buffer so that voltage stored on sample capacitor can be read out directly. In this design, each column has one low power charge amplifier, and output buffer's power is optimized. Besides, capacitance of sample capacitor is much larger than that of CSA's feedback capacitor, so the KTC noise is lower and the charge injection is suppressed while the output range is not impaired. This design is also applicable to window readout. The readout speed can reach 8MHz with power consumption lower than 50mW. A 320 × 320 ROIC with pixel size of 30 × 30 μm 2 has been designed and fabricated with a 0.35 μm DPTM CMOS process under 5v supply voltage.
Based on the forward gated diode recombination current, a method for direct characterizing interface traps in 60V STI lateral high voltage SOI MOSFETs was proposed. Thus the interface traps induced by off-state or hot...
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Based on the forward gated diode recombination current, a method for direct characterizing interface traps in 60V STI lateral high voltage SOI MOSFETs was proposed. Thus the interface traps induced by off-state or hot carrier stresses can be directly located by distinct peaks in the forward gated diode recombination current. The method was also investigated by 2D device simulation and reliability experiments.
A novel layout strategy for on-chip ESD protection application is presented to solve the non-uniformity turn-on phenomenon of multi-finger gate-grounded nMOS (GGnMOS). The multi-finger gates as well as drains and sour...
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A novel layout strategy for on-chip ESD protection application is presented to solve the non-uniformity turn-on phenomenon of multi-finger gate-grounded nMOS (GGnMOS). The multi-finger gates as well as drains and sources are connected in serrate type. The whole multi-finger device acts as singer finger with large gate width. After realized in 0.13μm craft and tested under TLP method, the It2 per unit channel width of the novel GGnMOSs are much higher than those of the traditional GGnMOSs by this simply approach.
Using an auxiliary quantizer before unity-STF SDM, a novel 3 rd -order dual-quantizer SDM with extended dynamic range is presented. With hybrid distributed feedback & feedforward paths and an internal feedforward ...
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Using an auxiliary quantizer before unity-STF SDM, a novel 3 rd -order dual-quantizer SDM with extended dynamic range is presented. With hybrid distributed feedback & feedforward paths and an internal feedforward path, a novel low-distortion 3 rd -order SDM with simple adder before quantizer is proposed as the unity-STF SDM. Simulations show their perfect immunity to non-idealities.
A silicon-controlled rectifier (SCR) device for on-chip ESD protection is proposed. The Anode pad of the device is directly connected to die drain of the embedded nMOS crossing the N-well P-substrate junction of the n...
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A silicon-controlled rectifier (SCR) device for on-chip ESD protection is proposed. The Anode pad of the device is directly connected to die drain of the embedded nMOS crossing the N-well P-substrate junction of the nMOS to achieve a high holding current. Thus, latch-up immune current of SCR type ESD protection device is achieved by this method.
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