The black multi-crystalline silicon(mc-Si) has been successfully produced by plasma immersion ion *** microstructure and the reflectance of the black mc-Si have been investigated by atomic force microscope and spect...
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The black multi-crystalline silicon(mc-Si) has been successfully produced by plasma immersion ion *** microstructure and the reflectance of the black mc-Si have been investigated by atomic force microscope and spectrophotometer,*** show that the black mc-Si exhibits a hillock structure with a low ***,with decreasing the diffusion temperature,the external quantum efficiency of the black mc-Si solar cell increases below 50 nm wavelength due to reduced surface *** optimal conversion effieciency of the black mc-Si solar cell is 15.50%at the diffusion temperature of 825 ℃.Furthermore,it is interesting to find that there are something different between black mc-Si and acid etched mc-Si on the impact of diffusion.
novel radio frequency single-dielectric-barrier-discharge atmospheric pressure plasma generator was designed and utilized to strip AZ9912 photo-resist (PR).
novel radio frequency single-dielectric-barrier-discharge atmospheric pressure plasma generator was designed and utilized to strip AZ9912 photo-resist (PR).
During the forming process of the free-standing structure or the functional cavity when releasing the high aspect ratio sacrificial layer, such structures tend to stick to the substrate due to capillary force. This pa...
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During the forming process of the free-standing structure or the functional cavity when releasing the high aspect ratio sacrificial layer, such structures tend to stick to the substrate due to capillary force. This paper describes the application of pull-in length conception as design rules to a novel 'dimpled' method in releasing sacrificial layer. Based on the conception of pull-in length in adhering Phenomenon, the fabrication and releasing sacrificial layer methods using micro bumps based on the silicon substrate were presented. According to the thermal isolation performances of one kind of micro electromechanical system device thermal shear stress sensor, the sacrificial layers were validated to be successfully released.
This paper presents a novel anti-shock bulk silicon etching apparatus for solving a universal problem which occurs when releasing the diaphragm (e.g. SiNx), that the diaphragm tends to be probably cracked by the imp...
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This paper presents a novel anti-shock bulk silicon etching apparatus for solving a universal problem which occurs when releasing the diaphragm (e.g. SiNx), that the diaphragm tends to be probably cracked by the impact of heatinginduced bubbles, the swirling of heating-induced etchant, dithering of the hand and imbalanced etchant pressure during the wafer being taken out. Through finite element methods, the causes of the diaphragm cracking are analysed. The impact of heating-induced bubbles could be the main factor which results in the failure stress of the SiNx diaphragm and the rupture of it. In order to reduce the four potential effects on the cracking of the released diaphragm, an anti-shock hulk silicon etching apparatus is proposed for using during the last etching process of the diaphragm release. That is, the silicon wafer is first put into the regular constant temperature etching apparatus or ultrasonic plus, and when the residual bulk silicon to be etched reaches near the interface of the silicon and SiNx diaphragm, within a distance of 50-80μm (the exact value is determined by the thickness, surface area and intensity of the released diaphragm), the wafer is taken out carefully and put into the said anti-shock silicon etching apparatus. The wafer's position is at the geometrical centre, also the centre of gravity of the etching vessel. An etchant outlet is built at the bottom. The wafer is etched continuously, and at the same time the etchant flows out of the vessel. Optionally, two symmetrically placed low-power heating resistors are put in the anti-shock silicon etching apparatus to quicken the etching process. The heating resistors' power should be low enough to avoid the swirling of the heating-induced etchant and the impact of the heating-induced bubbles on the released diaphragm. According to the experimental results, the released SiNx diaphragm thus treated is unbroken, which proves the practicality of the said anti-shock bulk silicon etching appar
Low power on-chip interconnect technique is important for deep submicron SOC design. In this paper, a novel low swing drivers scheme based on charge redistribution is proposed. Significant reduction in power dissipati...
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Low power on-chip interconnect technique is important for deep submicron SOC design. In this paper, a novel low swing drivers scheme based on charge redistribution is proposed. Significant reduction in power dissipation is achieved by dividing the full signal swing into several lower ones. The proposed circuits are especially suitable for driving multi-branch transmission wires by utilizing higher efficiency of charges. Compared with the reference design, the new scheme can reduce power dissipation by more than 66% as shown by HSPICE simulation while driving three branches. The proposed circuits have been fabricated and its effectiveness has been verified by measurement results.
A low-noise readout integrated circuit for high-energy particle detector is *** noise of charge sensitive amplifier was suppressed by using single-side amplifier and resistors as source ***-time semi-Gaussian filter i...
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A low-noise readout integrated circuit for high-energy particle detector is *** noise of charge sensitive amplifier was suppressed by using single-side amplifier and resistors as source ***-time semi-Gaussian filter is chosen to avoid switch *** peaking time of pulse shaper and the gain can be programmed to satisfy *** readout integrated circuit has been designed and fabricated using a 0.35 μm double-poly triple-metal CMOS *** results show the functions of the readout integrated circuit are *** equivalent noise charge with no detector connected is 500–700 e in the typical mode,the gain is tunable within 13–130 mV/fC and the peaking time varies from 0.7 to 1.6 μs,in which the average gain is about 20.5 mV/fC,and the linearity reaches 99.2%.
For interconnect between NoC (Network-on-Chip) routers, power consumption is high and data rates are limited when conventional transceivers are used. In this paper, a novel high-speed and low-power source-synchronous ...
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For interconnect between NoC (Network-on-Chip) routers, power consumption is high and data rates are limited when conventional transceivers are used. In this paper, a novel high-speed and low-power source-synchronous transceiver is proposed. An improved low-swing FIR (Finite Impulse Response) filter with resistive pre-emphasis in combination with a double-tail sense amplifier enables a achievable data-rate of 9Gb/s over a 2mm twisted differential interconnect, while consuming only 181fJ/b. By transmitting the clock signals with reduced swing, power consumption of the source-synchronous clock is reduced by 66%.
In this work, we investigate strain effects induced by the deposition of gate dielectrics on the valence band structures in Si (110) nanowire via the simulation of strain distribution and the calculation of a genera...
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In this work, we investigate strain effects induced by the deposition of gate dielectrics on the valence band structures in Si (110) nanowire via the simulation of strain distribution and the calculation of a generalized 6 × 6k .p strained valence band. The nanowire is surrounded by the gate dielectric. Our simulation indicates that the strain of the amorphous SiO2 insulator is negligible without considering temperature factors. On the other hand, the thermal residual strain in a nanowire with amorphous SiO2 insulator which has negligible lattice misfit strain pushes the valence subbands upwards by chemical vapour deposition and downwards by thermal oxidation treatment. In contrast with the strain of the amorphous SiO2 insulator, the strain of the HfO2 gate insulator in Si (110) nanowire pushes the valence subbands upwards remarkably. The thermal residual strain by HfO2 insulator contributes to the up-shifting tendency. Our simulation results for valence band shifting and warping in Si nanowires can provide useful guidance for further nanowire device design.
A unified microscopic principle is proposed to clarify resistive switching behaviors of transition metal oxide based resistive random access memories (RRAM) for the first time. In this unified microscopic principle, b...
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A unified microscopic principle is proposed to clarify resistive switching behaviors of transition metal oxide based resistive random access memories (RRAM) for the first time. In this unified microscopic principle, both unipolar and bipolar switching characteristics of RRAM are correlated with the distribution of localized oxygen vacancies in the oxide switching layer, which is governed by the generation and recombination with dissociative oxygen ions. Based on the proposed microscopic principle, an atomistic simulation method is developed to evaluate critical memory performance, and successfully conduct the device optimization. The experimental data are well in line with the developed simulation method.
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