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2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology

作者： Yu, Tao Wang, Runsheng Ding, Wei Huang, Ru Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University Beijing 100871 China

ISBN: (纸本)9781424457984

In this paper, the impacts of diameter-dependent annealing (DDA) effect on nanowire S/D extension random dopant fluctuations (SDE-RDF) in silicon nanowire MOSFETs (SNWTs) are investigated, in terms of electrostatic properties, source/drain series resistance (RSD), and driving current. The SDE-RDF induced variations of threshold voltage (Vth) and DIBL in SNWTs with different diameters are found to be modest and decrease as the diameters down-scale. However, SDE-RDF induced RSD variation in SNWTs is enhanced by abnormal DDA effects, which aggravates the drive current variations with the downscaling of SNWT diameter. The results also show that Vth is the dominant factor in ON/OFF current ratio variation while RSD dominates that of ON current. The tradeoff between RSD and Vth dominant current variations is discussed to give some guidelines for SDE-RDF-aware design in SNWTs. ©2010 IEEE.

关键词： Threshold voltage

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Analysis of LDMOS-SCR ESD protection device for 60V SOI BCD technology

Analysis of LDMOS-SCR ESD protection device for 60V SOI BCD ...

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2010 IEEE International Conference of Electron devices and Solid-State circuits, EDSSC 2010

作者： Zhang, Peng Wang, Yuan Jia, Song Zhang, Xing Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University Beijing 100871 China

ISBN: (纸本)9781424499977

A study of two major types of LDMOS-SCR electrostatic discharge protection devices for 60V SOI BCD technology is presented. The difference of the P-anode implant positions influences the triggering mechanism of the two types of devices. The relationship between I-V behavior under ESD and the device parameter is studied. Heat dissipation capability of the device is also presented. © 2010 IEEE.

关键词： Electrostatic devices

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Predictive modeling of capacitance and resistance in gate-all-around cylindrical nanowire MOSFETs for parasitic design optimization

Predictive modeling of capacitance and resistance in gate-al...

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2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology

作者： Xu, Qiumin Zou, Jibin Luo, Jieyin Wang, Runsheng Huang, Ru Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University Beijing 100871 China

ISBN: (纸本)9781424457984

This paper presents a predictive electrostatic capacitance and resistance compact model of multiple gate MOSFET with cylindrical conducting channels, taking into account parasitic effects, quantum confinement and quasi-ballistic effects. The model incorporates the dependence of channel length, gate height and width, gate-to-contact spacing, nanowire size, multiple channels, as well as 1-D ultra-narrow source/drain extension (SDE) doping profile. The proposed non-iterative electrostatic model is successfully verified, and can be used to predict nanowire-based circuit performance. Based on the analytical model, we can further examine which parasitic components are affecting the delay. Results revealed that Cside, Cof, Rsd, RQ are dominant factors and should be treated as a major design concern. Among all the parameters, Lsd, Tg and Ndop are essentially important in parasitic design optimization. By selectively modifying these parameters, parasitic effect is evidently reduced. ©2010 IEEE.

关键词： Nanowires

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Characterizing, modeling, and simulating soft error susceptibility in cell-based designs in highly scaled technologies

Characterizing, modeling, and simulating soft error suscepti...

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12th European Conference on Radiation and Its Effects on Component and Systems, RADECS 2011

作者： Li, Y.F. Li, M. Zhao, J.Y. Schrimpf, R.D. Fleetwood, D.M. Zhang, B. Wang, J.Q. Wang, D.L. Wang, Y. Accelicon Technologies Inc. 19925 Stevens Creek Blvd Cupertino CA 95014 United States Electrical Engineering and Computer Science Department Vanderbilt University VU Station B 351825 Nashville TN 37235-1825 United States State Key Laboratory of Electronic Thin Films and Integrated Devices University of Electronic Science and Technology of China Chengdu 610054 China Institute of Automation Chinese Academy of Science Beijing 100190 China Institute of Microelectronics Tsinghua University Beijing 100084 China

A systematic flow is described for characterizing, modeling, and simulating single event transient-induced soft errors in cell-based designs. Pulse broadening effects are quantified for a 65 nm CMOS process. © 20... 详细信息

ISBN: (纸本)9781457705878

关键词： Radiation hardening

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ATOMIC LAYER DEPOSITION HfO_(2)FILM USED AS BUFFER LAYER OF THE Pt/(Bi_(0.95)Nd_(0.05))(Fe_(0.95)Mn_(0.05))O_(3)/HfO_(2)/Si CAPACITORS FOR FeFET APPLICATION

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Journal of Advanced Dielectrics 2011年第3期1卷 369-377页

作者： DAN XIE TINGTING FENG YAFENG LUO XUEGUANG HAN TIANLING REN MARKUS BOSUND SHUO LI VELI-MATTI AIRAKSINEN HARRI LIPSANEN SEPPO HONKANEN Tsinghua National Laboratory for Information Science and Technology(TNList) Institute of Microelectronics Tsinghua UniversityBeijing 100084P.R.China Department of Micro and Nanosciences Aalto University School of Science and Technology Finland State Key Laboratory of Electronic Thin Films and Integrated Devices University of Electronic Science and Technology of ChinaChengdu 610054P.R.China

Neodymium and manganese doped BiFeO_(3)-(Bi_(0.95)Nd_(0.05))(Fe_(0.95)Mn_(0.05))O_(3)(BNFMO)ferro-electric film and HfO_(2)layer with different thickness were fabricated using metal-organic decomposition and atomic layer deposition(ALD)method,*** ferroelectric-insulator-semiconductor(MFIS)capacitors with 200 nm thick BNFMO and 5 nm thick HfO_(2)layer on silicon substrate have been prepared and *** is found that there is no distinct interdifusion and reaction occurring at the interface between BNFMO/HfO_(2)and HfO_(2)/*** capacitance-voltage(C-V)and leakage current properties of Pt/HfO_(2)/Si capacitors with different HfO_(2)thickness were *** MFIS structure showed clockwise C-V hysteresis loops due to the ferroelectric polarization of *** maximum memory window is 5 *** current of the Pt/BNFMO/HfO_(2)/Si capacitor was about 2.1×10^(-6)A/cm^(2)at an applied voltage of 4V.

关键词： ALD HfO_(2) BFO MFIS ferroelectric capacitor

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Nd-doped Bismuth Titanate based ferroelectric field effect transistor: Design, fabrication, and optimization

Nd-doped Bismuth Titanate based ferroelectric field effect t...

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IEEE Conference on Electron devices and Solid-State circuits

作者： Tingling Feng Dan Xie Yongyuan Zang Xaio Wu Yafeng Luo Tianling Ren Markus Bosund Shuo Li Veli-Matti Airaksinen Harri Lipsanen Seppo Honkanen Tsinghua National Laboratory for information Science and Technology (TNList) Institute of Microelectronics Tsinghua University Beijing China State Key Laboratory of Electronic Thin Final and Intergrated Devices University of Electronic science and Technology of China Chengdu China Electrical and Computer Engineering McGill University Montreal QUE Canada Department of micro and Nanosciences Aalto University of Science and Technology Finland

Ferroelectric field effect transistor (FeFET) is a promising candidate in nonvolatile memory application due to its fast read/write speed, nondestructive readout, and low power consumption. Since the poor retention characteristic can be improved by introducing insulator buffer layers between gate layer and FET channel region, more and more attentions are devoted to the realization and optimization of this novel memory device [1]. Traditional ferroelectric materials, such as PZT [2, 3] and SBT [4] based FeFETs are extensively studied and reported in the past decades. Recently, Nd-doped Bismuth Titanate B 3.15 Nd 0.85 Ti 3 O 12 (BNdT) with a large remnant polarization (2Pr=103μC/cm 2 ) and outstanding fatigue endurance was reported by Chon et al. [5], and many ferroelectric applications are being processed based on this brand new ferroelectric material [6, 7]. In this letter, we fabricated a BNdT based FeFET for the first time. The fundamental structural and electrical properties are investigated correspondingly.

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Characterizing, modeling, and simulating soft error susceptibility in cell-based designs in highly scaled technologies

Characterizing, modeling, and simulating soft error suscepti...

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European Conference on Radiation and its Effects on Components and Systems (RADECS)

作者： Y. F. Li M. Li J. Y. Zhao R. D. Schrimpf D. M. Fleetwood B. Zhang J. Q. Wang D. L. Wang Y. Wang Accelicon Technologies Inc. Cupertino CA USA Electrical Engineering and Computer Science Department Vanderbilt University Nashville TN USA State Key Laboratory of Electronic Thin Films and Integrated Devices University of Electronic Science and Technology Chengdu China Institute of Automation Chinese Academy of Sciences Beijing China Institute of Microelectronics Tsinghua University Beijing China

关键词： Boolean functions Data structures Pulse measurements Inverters Logic gates Delay SPICE

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Buffer design based on flow control in RapidIO

Buffer design based on flow control in RapidIO

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Asia Pacific Conference on Postgraduate Research in microelectronics & Electronics (PrimeAsia)

作者： Xiongbo Zhao Song Jia Yuan Wang Guirong Wu Fengfeng Wu Kai Yang Key Laboratory of Microelectronics Devices and Circuits Institute of Microelectronics Peking University Beijing China

RapidIO is an open standard that provides high-performance interconnect for chip-to-chip, board-to-board, and chassis-to-chassis communications. In this paper, we present an executable RapidIO interconnect in which an improved Buffer structure based on flow control is put forward. It helps to provide a smooth data flow, strong built-in error detection and error recovery mechanisms. It is tested to increase utilization and lower packet latency. And it can be applied to reliable and high speed embedded system communications.

关键词： Physical layer Embedded system Protocols Receivers Transmitters Integrated circuit interconnections Performance evaluation

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A novel nitrogen-doped SiOx resistive switching memory with low switching voltages

A novel nitrogen-doped SiOx resistive switching memory with ...

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2010 15th Silicon Nanoelectronics Workshop, SNW 2010

作者： Gao, Dejin Zhang, Lijie Huang, Ru Wang, Runsheng Wu, Dongmei Kuang, Yongbian Tang, Yu Yu, Zhe Wang, Albert Z. H. Wang, Yangyuan Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University 100871 China Dept. of Electrical Engineering University of California Riverside CA 92521 United States

ISBN: (纸本)9781424477272

In summary, a novel RRAM with the structure of Cu/SixO yNz/W was first fabricated and its characteristics are thoroughly investigated. The new device exhibited low switching voltages and low reset currents, demonstrating its potential for low-power applications. Repeatable unipolar resistive switching characteristics in terms of high off/on resistance ratio and good retention capability were observed. The switching mechanism of the device was analyzed and can be explained by the formation and rupture of vacancy-filaments.

关键词： Nitrogen

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Design of RapidIO logical core based on safety arbitration mechanisms

Design of RapidIO logical core based on safety arbitration m...

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Asia Pacific Conference on Postgraduate Research in microelectronics & Electronics (PrimeAsia)

作者： Wu Fengfeng Jia Song Yang Kai Zhao Xiongbo Wu Guirong Key Laboratory of Microelectronics Devices and Circuits (MOE) Institute of Microelectronics Peking University Beijing China

RapidIO is an emerging high-performance and point-to-point packetized interconnection technology. In this paper, the design of the logical core based on safety arbitration mechanisms is described in detail. The packing and unpacking of I/O Logical, Message Passing and Globally Shared Memory transactions are achieved. Excellent average data transfer rates, up to 7.8 bytes per cycle are reached in certain transactions with 256-byte data payloads, meanwhile the data efficiencies are more than 95%. Moreover, maintenance read transactions targeted at local capability and status registers can be executed in a lower latency compared with the reference design.

关键词： Maintenance engineering Delay Payloads Receivers Transmitters Registers Safety

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