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Characterizing, modeling, and simulating soft error susceptibility in cell-based designs in highly scaled technologies

Characterizing, modeling, and simulating soft error suscepti...

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European Conference on Radiation and its Effects on Components and Systems (RADECS)

作者： Y. F. Li M. Li J. Y. Zhao R. D. Schrimpf D. M. Fleetwood B. Zhang J. Q. Wang D. L. Wang Y. Wang Accelicon Technologies Inc. Cupertino CA USA Electrical Engineering and Computer Science Department Vanderbilt University Nashville TN USA State Key Laboratory of Electronic Thin Films and Integrated Devices University of Electronic Science and Technology Chengdu China Institute of Automation Chinese Academy of Sciences Beijing China Institute of Microelectronics Tsinghua University Beijing China

A systematic flow is described for characterizing, modeling, and simulating single event transient-induced soft errors in cell-based designs. Pulse broadening effects are quantified for a 65 nm CMOS process.

关键词： Boolean functions Data structures Pulse measurements Inverters Logic gates Delay SPICE

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Buffer design based on flow control in RapidIO

Buffer design based on flow control in RapidIO

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Asia Pacific Conference on Postgraduate Research in microelectronics & Electronics (PrimeAsia)

作者： Xiongbo Zhao Song Jia Yuan Wang Guirong Wu Fengfeng Wu Kai Yang Key Laboratory of Microelectronics Devices and Circuits Institute of Microelectronics Peking University Beijing China

RapidIO is an open standard that provides high-performance interconnect for chip-to-chip, board-to-board, and chassis-to-chassis communications. In this paper, we present an executable RapidIO interconnect in which an improved Buffer structure based on flow control is put forward. It helps to provide a smooth data flow, strong built-in error detection and error recovery mechanisms. It is tested to increase utilization and lower packet latency. And it can be applied to reliable and high speed embedded system communications.

关键词： Physical layer Embedded system Protocols Receivers Transmitters Integrated circuit interconnections Performance evaluation

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A novel nitrogen-doped SiOx resistive switching memory with low switching voltages

A novel nitrogen-doped SiOx resistive switching memory with ...

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2010 15th Silicon Nanoelectronics Workshop, SNW 2010

作者： Gao, Dejin Zhang, Lijie Huang, Ru Wang, Runsheng Wu, Dongmei Kuang, Yongbian Tang, Yu Yu, Zhe Wang, Albert Z. H. Wang, Yangyuan Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University 100871 China Dept. of Electrical Engineering University of California Riverside CA 92521 United States

ISBN: (纸本)9781424477272

In summary, a novel RRAM with the structure of Cu/SixO yNz/W was first fabricated and its characteristics are thoroughly investigated. The new device exhibited low switching voltages and low reset currents, demonstrating its potential for low-power applications. Repeatable unipolar resistive switching characteristics in terms of high off/on resistance ratio and good retention capability were observed. The switching mechanism of the device was analyzed and can be explained by the formation and rupture of vacancy-filaments.

关键词： Nitrogen

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Design of RapidIO logical core based on safety arbitration mechanisms

Design of RapidIO logical core based on safety arbitration m...

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Asia Pacific Conference on Postgraduate Research in microelectronics & Electronics (PrimeAsia)

作者： Wu Fengfeng Jia Song Yang Kai Zhao Xiongbo Wu Guirong Key Laboratory of Microelectronics Devices and Circuits (MOE) Institute of Microelectronics Peking University Beijing China

RapidIO is an emerging high-performance and point-to-point packetized interconnection technology. In this paper, the design of the logical core based on safety arbitration mechanisms is described in detail. The packing and unpacking of I/O Logical, Message Passing and Globally Shared Memory transactions are achieved. Excellent average data transfer rates, up to 7.8 bytes per cycle are reached in certain transactions with 256-byte data payloads, meanwhile the data efficiencies are more than 95%. Moreover, maintenance read transactions targeted at local capability and status registers can be executed in a lower latency compared with the reference design.

关键词： Maintenance engineering Delay Payloads Receivers Transmitters Registers Safety

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Tuning the threshold voltage of low voltage organic thin film transistor using light illumination

Tuning the threshold voltage of low voltage organic thin fil...

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2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology

作者： Shang, Liwei Liu, Ming Ji, Zhuoyu Chen, Yingpin Wang, Hong Key Laboratory of Nanofabrication and Novel Devices Integration Technology Institute of Microelectronics Chinese Academy of Sciences Beijing 100029 China

ISBN: (纸本)9781424457984

High and random voltages are big challenges for practical applications of organic thin film transistors (OTFTs). Herein, a route to achieve devices with both low operating voltages (Vop) and tunable threshold voltages (VTH) was proposed. The Vop was reduced to be less 3 V without lowering the mobility and the ratio of on/off current using a 30 nm Al2O3 insulator film fabricated by atomic layer deposition technology. And the VTH was tuned from -1.7 V to 3.8 V by using light illumination combined with voltage pulse on gate electrodes. The tuning range is nearly twice of the operating voltage. And the tuning process is highly reversible. Uniform VTH of OTFTs can be obtained without changing process or materials. ©2010 IEEE.

关键词： Threshold voltage

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Improved multi-loop SMASH sigma-delta modulator for wideband applications

Improved multi-loop SMASH sigma-delta modulator for wideband...

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IEEE Conference on Electron devices and Solid-State circuits

作者： Hongyi Li Yuan Wang Song Jia Xing Zhang Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University Beijing China

In this paper, a novel design method has been proposed to realize feed-forward low-distortion unity STF sigma-delta modulators which are the critical blocks in multi-loop SMASH structure. Using the method, a timing-relaxed stable unity STF 2nd-order modulator has been proposed in detail. After that, an extremely high-resolution SMASH 2(3b)-2(3b)-1(2b) has been suggested using the proposed stages. Extensive results prove the efficiency of this topology.

关键词： Switches Wideband Computer languages

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Simulation of line-edge roughness effects in silicon nanowire MOSFETs

Simulation of line-edge roughness effects in silicon nanowir...

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International Conference on Simulation of Semiconductor Processes and devices (SISPAD)

作者： Tao Yu Runsheng Wang Ru Huang Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University Beijing China

In this paper, the effects of nanowire (NW) line-edge roughness (LER) in gate-all-around (GAA) silicon nanowire MOSFETs (SNWTs) are investigated by 3-D statistical simulation in terms of both performance variation and mean value degradation. A physical model is developed for NW LER induced performance degradation in SNWTs for the first time. The results indicate large performance mean value degradations due to NW LER in SNWTs. However, the LER induced parameter variation is still acceptable. In addition, as the LER correlation length (Λ) scales beyond the gate length, new distribution of performance parameters is observed, which has dual-peaks rather than single in conventional Gaussian distribution. The optimization for NW LER parameters is given for SNWT design as well.

关键词： Logic gates Degradation Silicon Performance evaluation MOSFETs Integrated circuit modeling Solid modeling

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New observations of suppressed randomization in LER/LWR of Si nanowire transistors: Experiments and mechanism analysis

New observations of suppressed randomization in LER/LWR of S...

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International Electron devices Meeting (IEDM)

作者： Runsheng Wang Tao Yu Ru Huang Yujie Ai Shuangshuang Pu Zhihua Hao Jing Zhuge Yangyuan Wang Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University Beijing China

In this paper, the nanowire (NW) line-edge/width roughness (LER/LWR) effects in Si nanowire transistors (SNWTs) are investigated by both experiments and theoretical analysis. New LER/LWR characteristics are first observed in SNWTs, which exhibits suppressed randomization and enhanced systematic variation, rather than pure random LER/LWR in planar and FinFET devices. An improved characterization method is proposed to distinguish the random and systematic variation components in NW LER/LWR. For the first time, the effects of the key fabrication process on the NW LWR are studied in detail, including impacts of different oxidation temperature, NW channel orientations, and patterning techniques (hardmask trimming, spacer define and E-beam lithography). The results indicate that the spacer define method combined with self-limiting oxidation is beneficial for SNWTs. The mechanism of reducing the random variation in NW LER/LWR is analyzed, considering 2-D stress-retarded curvature-dependent oxidation. Taken into account the variation of quantum confined carrier profile, a physical device model is also developed, providing some guidelines for LER/LWR-hardening design of SNWTs.

关键词： Oxidation Systematics Correlation Silicon Degradation Temperature Temperature measurement

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Two Effective Single-Loop High-Performance Sigma-Delta Modulators Based on 0.13μm CMOS

Two Effective Single-Loop High-Performance Sigma-Delta Modul...

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2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology(第十届固态和集成电路技术国际会议 ICSICT-2010)

作者： Hongyi Li Yuan Wang Song Jia Xing Zhang Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University Beijing China

In this paper, two high-resolution medium-bandwidth single-loop 4th-order single-bit sigma-delta modulators using a feed-forward and a feedback topology respectively are implemented in 0.13μm CMOS technology. The oversampling ratio is 50 with 312.5kHz input bandwidth, 14.66-bit and 16.62-bit resolution have been reached. The two circuits each consume about 8-mW from a single 1.2V supply voltage. After simulation, under the same circuit conditions, feedback structure gives better performance than feed-forward one. The experiment result could be a useful reference for the topology choice.

关键词： sigma-delta modulator switch-capacitor (SC) integrator feedback topology feed-forward topology high-resolution

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A 14-bit 300MHz pipelined DEM DAC with enhanced dynamic linearity

A 14-bit 300MHz pipelined DEM DAC with enhanced dynamic line...

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Asia Pacific Conference on Postgraduate Research in microelectronics & Electronics (PrimeAsia)

作者： Zhao Junlei Wang Yuan Zhao Zhihui Jia Song Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University Beijing China

This paper presents a 14-bit digital-to-analog converter (DAC) with pipelined dynamic element matching to eliminate signal-dependent distortions and achieve good linearity at high sampling frequencies. A return-to-zero output stage is developed to enhance the dynamic linearity and increase the output impedance of current sources. And a novel current source array is employed to eliminate systematic and graded errors. The spurious-free dynamic range is 80.9dB at 312MS/s with a 150MHz input. The DAC is implemented in a 0.13-μm CMOS process, and consumes 48mW at 1.2-V power supply and 312MS/s.

关键词： Arrays Linearity Impedance Switches Encoding Systematics CMOS integrated circuits

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