This work presents a low-power low-cost CDR design for RapidIO SerDes. The design is based on phase interpolator, which is controlled by a synthesized standard cell digital block. Half-rate architecture is adopted to ...
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This work presents a low-power low-cost CDR design for RapidIO SerDes. The design is based on phase interpolator, which is controlled by a synthesized standard cell digital block. Half-rate architecture is adopted to lessen the problems in routing high speed clocks and reduce power. An improved half rate bang-bang phase detector is presented to assure the stability of the system. Moreover, the paper proposes a simplified control scheme for the phase interpolator to further reduce power and cost. The CDR takes an area of less than 0.05 m m 2 , and post simulation shows that the CDR has a RMS jitter of UI pp /32 (11.4 ps @3.125GBaud) and consumes 9.5 mW at 3.125 GBaud.
In this paper, several techniques which relax circuit requirements of building blocks are presented to effectively realize wideband high-resolution cascade sigma-delta modulator. Three cascade structures have been pro...
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In this paper, several techniques which relax circuit requirements of building blocks are presented to effectively realize wideband high-resolution cascade sigma-delta modulator. Three cascade structures have been proposed in this paper. First, a MASH 2-2 with feed-forward topology in both stages has been explained to obtain low-distortion property and remove subtraction Second, a flexible SMASH 2-2 has been proposed to choose appropriate coefficients for different requirements. Third, a SMASH 2-2 with feed-forward quantization noise self-coupled structure has been displayed to cancel quantization error of the preceding stage totally. Detailed simulation results and comparisons demonstrate the performance of these topologies.
A novel LDMOS-SCR device for electrostatic discharge protection of power device is presented. The device is able to be fabricated in SOI 40V LDMOS process without any extra mask. Due to the new structure, a proper and...
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ISBN:
(纸本)9781424457977
A novel LDMOS-SCR device for electrostatic discharge protection of power device is presented. The device is able to be fabricated in SOI 40V LDMOS process without any extra mask. Due to the new structure, a proper and controllable triggering voltage and fine heat dissipation capability are achieved.
This paper presents a predictive electrostatic capacitance and resistance compact model of multiple gate MOSFET with cylindrical conducting channels, taking into account parasitic effects, quantum confinement and quas...
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ISBN:
(纸本)9781424457977
This paper presents a predictive electrostatic capacitance and resistance compact model of multiple gate MOSFET with cylindrical conducting channels, taking into account parasitic effects, quantum confinement and quasi-ballistic effects. The model incorporates the dependence of channel length, gate height and width, gate-to-contact spacing, nanowire size, multiple channels, as well as 1-D ultra-narrow source/drain extension (SDE) doping profile. The proposed non-iterative electrostatic model is successfully verified, and can be used to predict nanowire-based circuit performance. Based on the analytical model, we can further examine which parasitic components are affecting the delay. Results revealed that Qside. Cof, Rsd RQ are dominant factors and should be treated as a major design concern. Among all the parameters, Lsd Tg and Ndop are essentially important in parasitic design optimization. By selectively modifying these parameters, parasitic effect is evidently reduced.
In this paper, the impacts of diameter-dependent annealing (DDA) effect on nanowire S/D extension random dopant fluctuations (SDE-RDF) in silicon nanowire MOSFETs (SNWTs) are investigated, in terms of electrostatic pr...
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ISBN:
(纸本)9781424457977
In this paper, the impacts of diameter-dependent annealing (DDA) effect on nanowire S/D extension random dopant fluctuations (SDE-RDF) in silicon nanowire MOSFETs (SNWTs) are investigated, in terms of electrostatic properties, source/drain series resistance (RSD), and driving current. The SDE-RDF induced variations of threshold voltage (Vth) and DIBL in SNWTs with different diameters are found to be modest and decrease as the diameters down-scale. However, SDE-RDF induced RSd variation in SNWTs is enhanced by abnormal DDA effects, which aggravates the drive current variations with the downscaling of SNWT diameter. The results also show that Vth is the dominant factor in ON/OFF current ratio variation while RSd dominates that of ON current. The tradeoff between RSd and Vth dominant current variations is discussed to give some guidelines for SDE-RDF-aware design in SNWTs.
For the gate last integration scheme, dummy poly silicon gate removal is one of the indispensable processes either for a high-k first or a high-k last route. In this paper, experimental results of dummy poly silicon g...
For the gate last integration scheme, dummy poly silicon gate removal is one of the indispensable processes either for a high-k first or a high-k last route. In this paper, experimental results of dummy poly silicon gate removal using TetraMethyl Ammonium Hydroxide (TMAH) chemical etching are presented. The preliminary results show that the poly silicon removal rate was highly sensitive to the wet etch conditions. By optimizing the wet etch conditions, high selectivity of poly silicon with respect to SiO2, Si3N4 and hafnium silicon oxynitride (HfSiON) was obtained. A gate trench of critical dimension (CD) of about 70 nm without poly silicon residue was fabricated using optimized conditions. The excellent etch capability of the optimized wet etch process was also demonstrated by controlling trench profiles.
Voltage pulse dependent resistive switching behavior during SET process in HfO2-based RRAM device is investigated. When a resistor is connected in series to RRAM during the SET process, the resistance uniformity can b...
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Voltage pulse dependent resistive switching behavior during SET process in HfO2-based RRAM device is investigated. When a resistor is connected in series to RRAM during the SET process, the resistance uniformity can be improved. Voltage pulse controlled resistance states were observed. This behavior may provide the new application with the new function circuits.
We calculate valence band structures and transport property of HfO 2 gate dielectric surrounded Ge (110) nanowire with a radial force at the boundary of the insulator. The radial force pushes the valence subbands dow...
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ISBN:
(纸本)9781424435432;9781424435449
We calculate valence band structures and transport property of HfO 2 gate dielectric surrounded Ge (110) nanowire with a radial force at the boundary of the insulator. The radial force pushes the valence subbands downwards. Most of hole effective masses of top five subbands decrease and densities of states' peaks move down as the force increases. The hole mobility in Ge (110) NW significantly increases with higher force values.
In this paper, topology of gyrator-C active inductors are briefly reviewed. A novel structure of multi-band RF active inductor using transistors is presented. Issues of the active inductor related to stability, Q-enha...
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A simple method was developed to generate nanolamellas of CuTCNQ based on the principle of "spontaneous electrolysis". The nanolamellas were identified to belong to phase I of CuTCNQ. Intermediate products b...
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