In this paper, we investigate the combined effects of total ionizing dose (TID) and negative bias temperature instability (NBTI) on deep sub-micron pMOSFETs. It is found that the high temperature of the NBT stress ind...
In this paper, we investigate the combined effects of total ionizing dose (TID) and negative bias temperature instability (NBTI) on deep sub-micron pMOSFETs. It is found that the high temperature of the NBT stress induces an annealing effect by removing part of the radiation-induced positive charges. If we choose a relatively low temperature to avoid the annealing effect, a remarkable radiation acceleration effect on device degradation is observed and the lifetime of pMOSFETs significantly reduces due to more radiation-induced new hole traps in the oxide. However, the acceleration effect seems independent of the oxide electric field during NBT stress. The work in this paper indicates that it is important to choose proper NBT stress conditions if we use NBTI to predict the lifetime of the pMOSFETs which operate in the radiation environments.
A low-noise readout integrated circuit for high-energy particle detector is presented. The noise of charge sensitive amplifier was suppressed by using single-side amplifier and resistors as source ***-time semi-Gaussi...
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A low-noise readout integrated circuit for high-energy particle detector is presented. The noise of charge sensitive amplifier was suppressed by using single-side amplifier and resistors as source ***-time semi-Gaussian filter is chosen to avoid switch noise. The peaking time of pulse shaper and the gain can be programmed to satisfy multi-application. The readout integrated circuit has been designed and fabricated using a 0.35 μm double-poly triple-metal CMOS technology. Test results show the functions of the readout integrated circuit are correct. The equivalent noise charge with no detector connected is 500-700 e in the typical mode, the gain is tunable within 13-130 mV/fC and the peaking time varies from 0.7 to 1.6 μs, in which the average gain is about 20.5 mV/fC, and the linearity reaches 99.2%.
The temperature field in the vertical metalorganic chemical vapor deposition （MOCVD） reactor chamber used for the growth of GaN materials is studied using the finite element analysis method （FEM）. The effects of t...
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The temperature field in the vertical metalorganic chemical vapor deposition （MOCVD） reactor chamber used for the growth of GaN materials is studied using the finite element analysis method （FEM）. The effects of the relative position between the coils and the middle section of the susceptor, the radius of the coil, and the height of the susceptor on heating condition are analyzed. All simulation results indicate that the highest heating efficiency can be obtained under the conditions that the coil distributes symmetrically in the middle section of the susceptor and the ratio of the height of the susceptor to that of the coil is three-quarters. Furthermore, the heating efficiency is inversely proportional to the radius of the coil.
A readout integrated circuit for high energy particle detectors is presented. The circuit designed is composed of a Charge Sensitive Amplifier (CSA), a pulse shaper with four selectable peaking time, and an output sta...
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The current slump of different recipes of SiN~ passivated AIGaN/GaN high electron mobility transistors （HEMTs） is investigated. The dc and pulsed current-voltage curves of AIGaN/GaN HEMTs using different recipes are...
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The current slump of different recipes of SiN~ passivated AIGaN/GaN high electron mobility transistors （HEMTs） is investigated. The dc and pulsed current-voltage curves of AIGaN/GaN HEMTs using different recipes are analyzed. It is found that passivation leakage has a strong relationship with NH3 flow in the plasma-enhanced chemical vapor phase deposition process, which has impacted on the current collapse of SiNs passivated devices. We analyze the pulsed IDS -- VDS characteristics of different recipes of SiNx passivation devices for different combinations of gate and drain quiescent biases （VGso, VDSO） of （0, 0）, （-6, 0）, （-6, 15） and （0, 15）V. The possible mechanisms are the traps in SiNxpassivation capturing the electrons and the surface states at the SiNx/AIGaN interface, which can affect the channel of two-dimensional electron gas and cause the current collapse.
The impacts of three different strain configurations on both DC and RF performance of n-type silicon nanowire transistors (n-SNWTs) are investigated. It is found that the longitudinal tensile strain is the most effici...
The impacts of three different strain configurations on both DC and RF performance of n-type silicon nanowire transistors (n-SNWTs) are investigated. It is found that the longitudinal tensile strain is the most efficient in improving the driving current and RF performance of n-SNWTs under the same stress value. In addition, the transverse compressive strain is also beneficial to the performance improvement, and can be combined in the stress engineering. Particularly, transverse biaxial compressive strain can effectively enhance the driving current, and at the same time slightly decrease the off-current of n-SNWT, which is beneficial for high speed and low power design. The results indicate that, due to the unique feature of gate-all-around 1D structure, the strain design in SNWTs, especially the combination of longitudinal strain and transverse strain, can be specially optimized for better device performance.
Silicon nanocrystals synthesized by electron beam (e-beam) evaporation of Si and SiO2 mixture are studied. Rutherford backscattering spectrometry of the as-deposited Si-rich silicon dioxide or oxide (SRO) thin film sh...
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Silicon nanocrystals synthesized by electron beam (e-beam) evaporation of Si and SiO2 mixture are studied. Rutherford backscattering spectrometry of the as-deposited Si-rich silicon dioxide or oxide (SRO) thin film shows that after evaporation, the Si and SiO2 concentration is well kept, indicating that the e-beam evaporation is suitable for evaporating mixtures of Si and SiO2. The SRO thin films are annealed at different temperatures for two hours to synthesize silicon nanocrystals. For the sample annealed at 1050℃, silicon nanocrystals with different sizes and the mean diameter of 4.5 nm are evidently observed by high resolution transmission electron microscopy (HRTEM). Then the Raman scattering and photoluminescence spectra arising from silicon nanocrystals are further confirmed the above results.
Several μ-bridge structures for InP-based heterojunction bipolar transistors （HBTs） are reported. The radio frequency measurement results of these InP HBTs are compared with each other. The comparison shows that μ...
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Several μ-bridge structures for InP-based heterojunction bipolar transistors （HBTs） are reported. The radio frequency measurement results of these InP HBTs are compared with each other. The comparison shows that μ-bridge structures reduce the parasites and double p-bridge structures have a better effect. Due to the utilization of the double/^-bridges, both the cutoff frequency fτ and also the maximum oscillation frequency fτ of the 2 × 12.5 μm2 InP/InGaAs HBT reach nearly 160 GHz. The results also show that the μ-bridge has a better effect in increasing the high frequency performance of a narrow emitter InP HBT.
A new architecture of digital processors for passive UHF radio-frequency identification tags is proposed. This architecture is based on ISO/IEC 18000-6C and targeted at ultra-low power consumption. By applying methods...
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A new architecture of digital processors for passive UHF radio-frequency identification tags is proposed. This architecture is based on ISO/IEC 18000-6C and targeted at ultra-low power consumption. By applying methods like system-level power management, global clock gating and low voltage implementation, the total power of the design is reduced to a few microwatts. In addition, an innovative way for the design of a true RNG is presented, which contributes to both low power and secure data transaction. The digital processor is verified by an integrated FPGA platform and implemented by the Synopsys design kit for ASIC flows. The design fits different CMOS technologies and has been taped out using the 2P4M 0.35 μm process of Chartered Semiconductor.
In this paper, we demonstrate a Monte Carlo simulator for ambipolar Schottky barrier MOSFETs which includes tunneling and thermal emission of electrons and holes and the appropriate treatment of carrier transport at n...
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