A new structure 288x4 CMOS time delay and integration(TDI) readout integrated circuit(ROIC) is presented in this *** TDI function is implemented using an integration and storage circuit array and a charge amplifier wi...
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A new structure 288x4 CMOS time delay and integration(TDI) readout integrated circuit(ROIC) is presented in this *** TDI function is implemented using an integration and storage circuit array and a charge amplifier with the advantages of low power and compact *** experimental chip has been designed and fabricated in 0.5μm double-poly-three-metal CMOS ***-directional TDI,defective element deselection and two-gain option(1.015pC/2.03pC) functions have been realized in the experimental chip and measurement results at liquid nitrogen temperature indicated that all functions were correct and performance satisfied the requirement of long waveform *** readout speed of each out can reach 5MHz and the dynamic range is 75.6dB.
In this paper,a simple low-cost sub-50 nm silicon fin patterning technology is proposed and experimentally *** technology is based on a micro-meter level lithography equipment,that is,it does not need any critical pho...
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In this paper,a simple low-cost sub-50 nm silicon fin patterning technology is proposed and experimentally *** technology is based on a micro-meter level lithography equipment,that is,it does not need any critical photolithographic *** masking layer for fin formation is the nitride caped oxide layer which is reduced in width from sub-micrometer scale to nano-meter scale through a lateral etching in *** etching rate is shown to slow down as the etching process goes on.A nano-scale oxide hard mask can be achieved after the nitride is *** the cross-sectional view and top view of the etching process are shown by SEM *** indicate the simple patterning way is of low cost and under good control,and applicable to FinFET technology.
The performance of the n-channel Schottky barrier MOSFET with asymmetric barrier height at source/drain (A-SBFET) was numerically *** impact factors on the performance are *** results suggest the on-state characterist...
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The performance of the n-channel Schottky barrier MOSFET with asymmetric barrier height at source/drain (A-SBFET) was numerically *** impact factors on the performance are *** results suggest the on-state characteristics of the devices are mainly determined by the source-side barrier height (SBH).Increasing SBH or decreasing body thickness can optimize the sub-threshold slope,and decreasing SBH can enhance the on-state current.
ZnO-based thin-film transistors(TFT) have been fabricated on p-Si(100) substrates by radio frequency(rf) magnetron sputtering at room temperature with a bottom gate *** XRD and SEM show that ZnO films had high crystal...
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ZnO-based thin-film transistors(TFT) have been fabricated on p-Si(100) substrates by radio frequency(rf) magnetron sputtering at room temperature with a bottom gate *** XRD and SEM show that ZnO films had high crystalline *** ZnO films present an average optical transmission(including the glass substrate) of 80%in the visible part of the spectrum. The electrical properties of ZnO-based TFTs were investigated by I-V and I-V *** ZnO TFT operates in the enhancement mode with a channel mobility of 6.86 cm/V ? *** combination of transparency,high channel mobility and room temperature processing makes the ZnO-TFT a very promising low cost optoelectronic device for the next generation of flat panel display(FDP).
A front-end ASIC for semiconductor radiation detectors is *** is composed of a Charge Sensitive Amplifier(CSA),a pulse shaper,and a Peak Detect and Hold(PDH) ***-resistor is used as source degeneration component to re...
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A front-end ASIC for semiconductor radiation detectors is *** is composed of a Charge Sensitive Amplifier(CSA),a pulse shaper,and a Peak Detect and Hold(PDH) ***-resistor is used as source degeneration component to reduce the noise of current source in the *** ASIC has been designed in a 0.5um CMOS DPTM technology and tested with Verigy *** gain(PDH excluded) is 78.5mV/fC and the Equivalent Noise Charge(ENC) with detector disconnected is *** power dissipation without the output buffer is about 2.6mW.
With the increased use of FPGA in widespread applications,its' size and speed has been rapidly increased,so more and more problems associated with performance defects are *** defects such as delay defects will not...
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With the increased use of FPGA in widespread applications,its' size and speed has been rapidly increased,so more and more problems associated with performance defects are *** defects such as delay defects will not lead to a functional fault, but will limit the frequency of the *** Stuck-at testing has not been sufficient to guarantee the reliability and quality,so testing delay fault becomes *** this paper,in order to improve the efficiency and coverage of delay test,we first select the most suitable delay fault model for FPGAs,which is a good simulation for the actual *** the same time we proposed a new configuration on the basis of *** method takes full advantage of the FPGAs' reconfiguration *** not only omits complex test pattern generation,but also optimizes the BIST circuits to minimize the area cost, and reaches higher fault *** verify the theory, we use Xilinx vertex4 devices on the experimental test, and achieved approving results.
Low-energy electron beam lithography has a variety of *** traditional electron scattering model consisting of Rutherford elastic scattering cross section and Bethe continuous slowing down approximation formula are not...
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Low-energy electron beam lithography has a variety of *** traditional electron scattering model consisting of Rutherford elastic scattering cross section and Bethe continuous slowing down approximation formula are not suitable for low-energy electron beam lithography.A more accurate physical model describing the low-energy electron scattering processes was proposed in this *** Monte Carlo method was used to simulate the complex scattering processes of Gaussian-distribution low-energy electron beam in the target of thin film on thick *** simulation results show that low-energy electron beam lithographyhas advantages of high throughput,low proximity effects and small damage to the underlying *** is in agreement with the conclusion got from Lee et al's and Peterson et al's experiments.
In this paper,we propose a simple but effective method to reduce the power in the design of the Speed Negotiation Algorithrn(SNA).Based on thoroughly analyzing the algorithm and the results of simulation,we identify t...
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In this paper,we propose a simple but effective method to reduce the power in the design of the Speed Negotiation Algorithrn(SNA).Based on thoroughly analyzing the algorithm and the results of simulation,we identify the large timers,the most commonly used in the SNA,as the most power consuming *** paper further develops a partition algorithm to tackle the power issue of the large *** the proposed method, we can reduce the power by 30%as opposed to only 19%if directly applying clock-gating methodology. Combined with clock-gating methodology,we can get 38%reduction in power with no more than 5%increase in area.
A 6-bit 200 Msps Folding/Interpolating analog to digital converter (ADC) with a novel dynamic encoder based on Rom theory is presented. The Precharge & Evaluate dynamic circuit is employed in the novel encoder and...
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ISBN:
(纸本)9781424421855
A 6-bit 200 Msps Folding/Interpolating analog to digital converter (ADC) with a novel dynamic encoder based on Rom theory is presented. The Precharge & Evaluate dynamic circuit is employed in the novel encoder and the bit synchronization logic to achieve high speed and reduce power dissipation. Realized in SMIC 0.35 um digital CMOS process, the whole ADC consumes only 35 mW at a 3.3 V voltage supply.
An efficient encoding scheme is proposed for folding ADC. In the encoder, XOR-OR encoding algorithm and dynamic domino circuit are adopted. A novel method for wide-range error correction and bit synchronization is pre...
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ISBN:
(纸本)9781424421855
An efficient encoding scheme is proposed for folding ADC. In the encoder, XOR-OR encoding algorithm and dynamic domino circuit are adopted. A novel method for wide-range error correction and bit synchronization is presented. Simulation results show that the proposed encoder has several advantages: high speed, low power dissipation and small chip area.
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