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Theoretical study of low-energy electron penetration in resist-substrate target by Monte Carlo simulation

Theoretical study of low-energy electron penetration in resi...

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2008 9th International Conference on Solid-State and Integrated-Circuit Technology

作者： Liming Ren Baoqin Chen Ru Huang Xing Zhang Key Laboratory of Microelectronic Devices and Circuits Institute of MicroelectronicsPeking University Institute of Microelectronics of the Chinese Academy of Sciences

Low-energy electron beam lithography has a variety of *** traditional electron scattering model consisting of Rutherford elastic scattering cross section and Bethe continuous slowing down approximation formula are not suitable for low-energy electron beam lithography.A more accurate physical model describing the low-energy electron scattering processes was proposed in this *** Monte Carlo method was used to simulate the complex scattering processes of Gaussian-distribution low-energy electron beam in the target of thin film on thick *** simulation results show that low-energy electron beam lithographyhas advantages of high throughput,low proximity effects and small damage to the underlying *** is in agreement with the conclusion got from Lee et al's and Peterson et al's experiments.

关键词： Theoretical study of low-energy electron penetration in resist-substrate target by Monte Carlo simulation Carlo Monte

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A Method to Lower Power in Speed Negotiation Algorithm of Fiber Channel

A Method to Lower Power in Speed Negotiation Algorithm of Fi...

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2008 9th International Conference on Solid-State and Integrated-Circuit Technology

作者： Jie Jin Dun Shan Yu Xiao Xin Cui Key Laboratory of Microelectronic Devices and Circuits.Institute of Microelectronics Peking University

In this paper,we propose a simple but effective method to reduce the power in the design of the Speed Negotiation Algorithrn(SNA).Based on thoroughly analyzing the algorithm and the results of simulation,we identify the large timers,the most commonly used in the SNA,as the most power consuming *** paper further develops a partition algorithm to tackle the power issue of the large *** the proposed method, we can reduce the power by 30%as opposed to only 19%if directly applying clock-gating methodology. Combined with clock-gating methodology,we can get 38%reduction in power with no more than 5%increase in area.

关键词： A Method to Lower Power in Speed Negotiation Algorithm of Fiber Channel

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Efficient encoding scheme for folding ADC

Efficient encoding scheme for folding ADC

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International Conference on Solid-State and Integrated Circuit Technology

作者： Zhen Liu Song Jia Yuan Wang Lijiu Ji Xing Zhang Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University China

ISBN: (纸本)9781424421855

An efficient encoding scheme is proposed for folding ADC. In the encoder, XOR-OR encoding algorithm and dynamic domino circuit are adopted. A novel method for wide-range error correction and bit synchronization is presented. Simulation results show that the proposed encoder has several advantages: high speed, low power dissipation and small chip area.

关键词： Encoding Error correction Power dissipation Voltage microelectronics Circuit simulation Logic circuits Read only memory Binary codes Timing

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Optimization of explicit-pulsed flip-flops for high performance

Optimization of explicit-pulsed flip-flops for high performa...

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International Conference on Solid-State and Integrated Circuit Technology

作者： Xiaoyang Zhang Song Jia Yuan Wang Ganggang Zhang Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University China

ISBN: (纸本)9781424421855

Two novel structures for explicit-pulsed flip-flops are proposed in this paper. The charging and discharging time are greatly reduced due to the lower capacitive load of interval nodes in the new structures, and the short circuit power consumption is diminished by overcoming the race problem as well. Simulation results also indicate the new structures are ideal for high-speed and low-power digital design.

关键词： Flip-flops Clocks Latches Switches Energy consumption Circuit stability Sampling methods Pulse generation Master-slave microelectronics

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On the effect of scattering in Schottky Barrier MOSFETs

On the effect of scattering in Schottky Barrier MOSFETs

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IEEE Conference on Electron devices and Solid-State circuits

作者： Lang Zeng Xiao Yan Liu Gang Du Jin Feng Kang Ru Qi Han Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University China

In this paper, we performed a simulation on a 45-nm UTB SOI Schottky Barrier MOSFETs using our two dimensional Ensemble full band Monte Carlo simulator to evaluate the effect of scattering in Schottky Barrier MOSFETs (SB FETs). The carrier transport details for both ballistic case and scattering case are simulated and analyzed. The scattering plays a less important role on the performance in SB FETs than in conventional highly doped S/D MOSFETs. Based on our analysis, the inappropriate of Natoripsilas ballistic transport model applied to SB FETs is revealed and the reason is due to the existence of non-local tunneling. Further development of the quasi ballistic model is necessary to include this non-local effect.

关键词： Schottky barriers MOSFETs FETs Optical scattering Acoustic scattering Ballistic transport Monte Carlo methods Electromagnetic compatibility microelectronics Performance evaluation

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A low power ROIC design for 1024×1024 IRFPA 9th

A low power ROIC design for 1024×1024 IRFPA

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International Conference on Solid-State and Integrated Circuit Technology

作者： Chang Liu Wengao Lu Zhongjian Chen Jing Li Yacong Zhang Lijiu Ji Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University China

ISBN: (纸本)9781424421855

A low power Read-Out Integrated Circuit (ROIC) for a short-wave Infra-Red Focal Plane Array (IRFPA) is designed as a prototype for 1024×1024 image system. Ripple integration and readout scheme as well as highly efficient power management is introduced to this design in order to decrease total power dissipation. To overcome the charge sharing problem caused by this low power readout scheme, novel low input capacitance column amplifier is proposed. The Data rate is about 10 M/s per channel, with a total power dissipation of 56 mW.

关键词： Power dissipation Capacitors Switches Linearity Detectors microelectronics Prototypes Parasitic capacitance MOSFET circuits Cooling

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A 900MHz UHF RFID reader transceiver in 0.18μm CMOS technology

A 900MHz UHF RFID reader transceiver in 0.18μm CMOS technol...

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International Conference on Solid-State and Integrated Circuit Technology

作者： Le Ye Huailin Liao Fei Song Jiang Chen Huilin Xiao Ruiqiang Liu Junhua Liu Xinan Wang Yangyuan Wang Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University China

ISBN: (纸本)9781424421855

This paper presents a UHF band (840 MHz~925 MHz) RFID reader transceiver design for the protocols of EPC Class-1 Gen-2 and ISO/IEC 18000-6C. The architecture and modules for the proposed transceiver are described and implemented in a standard 0.18 μm CMOS process. To suppress the leakage signal from transmitter to receiver, directional coupler and leakage cancellation circuit are introduced in the transceiver. A mixer with common-gate capacitor-cross-coupled input stage and vertical NPN switching stage is introduced to satisfy wideband matching and reduce 1/f noise corner. The transceiver, with an on-chip power-amplifier (PA) driver to drive off-chip PA, supports DSB-ASK, SSB-ASK and PR-ASK modulation schemes. A sigma-delta PLL is also implemented for 250 kHz channel hopping. Measurement results are given. Mixer achieves -8dBm P1 dB and 6.25 dB noise figure, phase noise of PLL is -127 dBc/Hz @ 1 MHz offset and settling time of channel hopping is within 30 μs. Settling time of killing leakage is less than 15 μs. The sensitivity of receiver can be -81dBm @ 40 kHz link frequency (LF). The total silicon area of the transceiver is 13 mm 2 , and draws 75 mA for 1.8 V supply voltage.

关键词： CMOS technology Radiofrequency identification Transceivers Phase locked loops Protocols ISO standards IEC standards CMOS process Transmitters Directional couplers

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Low power Folding/Interpolating ADC with a novel dynamic encoder based on ROM theory

Low power Folding/Interpolating ADC with a novel dynamic enc...

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International Conference on Solid-State and Integrated Circuit Technology

作者： Jilei Yin Yuan Wang Song Jia Zhen Liu Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University China

ISBN: (纸本)9781424421855

A 6-bit 200 Msps Folding/Interpolating analog to digital converter (ADC) with a novel dynamic encoder based on Rom theory is presented. The Precharge & Evaluate dynamic circuit is employed in the novel encoder and the bit synchronization logic to achieve high speed and reduce power dissipation. Realized in SMIC 0.35 um digital CMOS process, the whole ADC consumes only 35 mW at a 3.3 V voltage supply.

关键词： Read only memory Voltage Logic circuits Power dissipation Logic arrays microelectronics Analog-digital conversion Signal generators Binary codes Tail

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An acquisition circuit in Global Positioning System receivers

An acquisition circuit in Global Positioning System receiver...

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International Conference on Solid-State and Integrated Circuit Technology

作者： Xiaoxin Cui Chungan Peng Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University China

ISBN: (纸本)9781424421855;9781424421862

The conventional matched filter structures are investigated in this paper. An acquisition circuit based on the polyphase form matched filter in Global Positioning System (GPS) receiver is provided. At the cost of less hardware resource, the significant advantage in the speed of synchronization is offered. For 32×128 polyphase form matched filter, the critical path delay approximately reduces 1/2, the sample frequency would be double.

关键词： circuits Global Positioning System Frequency synchronization Matched filters Signal generators Hardware Shift registers Delay Satellites Glands

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A CMOS TDI readout circuit for infrared focal plane array

A CMOS TDI readout circuit for infrared focal plane array

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International Conference on Solid-State and Integrated Circuit Technology

作者： Zhongjian Chen Wengao Lu Ju Tang Yacong Zhang Cao Junmin Lijiu Ji Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University China

ISBN: (纸本)9781424421855

A new structure 288 × 4 CMOS time delay and integration (TDI) readout integrated circuit (ROIC) is presented in this paper. The TDI function is implemented using an integration and storage circuit array and a charge amplifier with the advantages of low power and compact layout. An experimental chip has been designed and fabricated in 0.5 ¿m double-poly-three-metal CMOS technology. Bi-directional TDI, defective element deselection and two-gain option (1.015 pC/2.03 pC) functions have been realized in the experimental chip and measurement results at liquid nitrogen temperature indicated that all functions were correct and performance satisfied the requirement of long waveform IRFPA. The readout speed of each out can reach 5 MHz and the dynamic range is 75.6 dB.

关键词： Circuit testing Bidirectional control Detectors microelectronics Delay effects CMOS technology Systolic arrays Switches Timing Signal detection

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