Capacitor composed of single crystalline Gd 2 O 3 on Si(100) with Pt top electrode was fabricated by molecular beam epitaxy. We present a systematic study of electrical properties of as-grown single crystalline Pt/Gd...
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Capacitor composed of single crystalline Gd 2 O 3 on Si(100) with Pt top electrode was fabricated by molecular beam epitaxy. We present a systematic study of electrical properties of as-grown single crystalline Pt/Gd 2 O 3 /Si(100). Three capacitors with different thickness are used for electrical evaluation. The EOT of the samples are estimated to be 0.7 nm, 1.2 nm and 1.8 nm respectively. Work function of Pt on Gd 2 O 3 is pinned at 4.75 eV and due to the lattice mismatch between Gd 2 O 3 , the interface state density is in the level of 10 13 extracted by Terman and conductance methods.
The latest progress in the growth technologies of silicon nano-wire, growth in vapor-liquid-solid( VLS) phases in particular, and its growth mechanisms were tentatively reviewed. Discussions centered on the favorable ...
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The latest progress in the growth technologies of silicon nano-wire, growth in vapor-liquid-solid( VLS) phases in particular, and its growth mechanisms were tentatively reviewed. Discussions centered on the favorable properties, including the novel electrical, optical and magnetic properties, and the potential applications of Si nanowires and Si nano-wires arrays, as the quasi one dimensional semi-conducting optoelectronic materials, in fabrication of devices, such as the field effect devices, single electron memory devices, photo-detection devices, field emission devices, nano-meter sensors and high efficient, light-emittiong devices, as well as the integration technology. Besides, the latest growth technologies of Si nano-wires, such as the metal-catalytic growth (Au, Fe, and Al), and its oxide-assisted growth based on VSL mechanism were introduced and reviewed. The scenarios of the silicon nanowire research and development were also predicted.
Capacitor composed of single crystalline Gd2O3 on Si(100) with Pt top electrode was fabricated by Molecular Beam Epitaxy. We present a systematic study of electrical properties of as-grown single crystalline Pt/Gd2O3/...
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Capacitor composed of single crystalline Gd2O3 on Si(100) with Pt top electrode was fabricated by Molecular Beam Epitaxy. We present a systematic study of electrical properties of as-grown single crystalline Pt/Gd2O3/Si(100). Three capacitors with different thickness are used for electrical evaluation. The EOT of the samples are estimated to be 0.7 nm, 1.2 nm and 1.8 nm respectively. Work function of Pt on Gd2O3 is pinned at 4.75 eV and due to the lattice mismatch between Gd2O3, the interface state density is in the level of 1013 extracted by Terman and conductance methods.
GaAs （001） substrates are patterned by electron beam lithography and wet chemical etching to control the nucleation of lnAs quantum dots （QDs）. InAs dots are grown on the stripe-patterned substrates by solid sourc...
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GaAs （001） substrates are patterned by electron beam lithography and wet chemical etching to control the nucleation of lnAs quantum dots （QDs）. InAs dots are grown on the stripe-patterned substrates by solid source molecular beam epitaxy. A thick buffer layer is deposited on the strip pattern before the deposition of InAs. To enhance the surface diffusion length of the In atoms, InAs is deposited with low growth rate and low As pressure. The AFM images show that distinct one-dimensionally ordered InAs QDs with homogeneous size distribution are created, and the QDs preferentiMly nucleate along the trench. With the increasing amount of deposited InAs and the spacing of the trenches, a number of QDs are formed beside the trenches. The distribution of additional QDs is long-range ordered, always along the trenchs rather than across the spacing regions.
作者：
王俊平郝跃张俊明Microelectronics Institute
Key Laboratory of Ministry of Education for Wide Band-Gap Semiconductor Materials and Devices Xidian University Xi'an 710071 China
In the existing models of estimating the yield and critical area, the defect outline is usually assumed to be circular, but the observed real defect outlines are irregular in shape. In this paper, estimation of the yi...
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In the existing models of estimating the yield and critical area, the defect outline is usually assumed to be circular, but the observed real defect outlines are irregular in shape. In this paper, estimation of the yield and critical area is made using the Monte Carlo technique and the relationship between the errors of yield estimated by circular defect and the rectangle degree of the defect is analysed. The rectangular model of a real defect is presented, and the yield model is provided correspondingly. The models take into account an outline similar to that of an original defect, the characteristics of two-dimensional distribution of defects, the feature of a layout routing, and the character of yield estimation. In order to make the models practicable, the critical area computations related to rectangular defect and regular （vertical or horizontal） routing are discussed. The critical areas associated with rectangular defect and non- regular routing are developed also, based on the mathematical morphology. The experimental results show that the new yield model may predict the yield caused by real defects more accurately than the circular model. It is significant that the yield is accurately estimated using the proposed model for IC metals.
The diffusion behaviours of vanadium implanted p- and n-type 4H-SiC are investigated by using the secondary ion mass spectrometry （SIMS）. Significant redistribution, especially out-diffusion of vanadium towards the ...
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The diffusion behaviours of vanadium implanted p- and n-type 4H-SiC are investigated by using the secondary ion mass spectrometry （SIMS）. Significant redistribution, especially out-diffusion of vanadium towards the sample surface is not observed after 1650 ℃annealing for both p- and n-type samples. Atomic force microscopy （AFM） is applied to the characterization of surface morphology, indicating the formation of continuous long furrows running in one direction across the wafer surface after 1650 ℃ annealing. The surface roughness results from the evaporation and re-deposition of Si species on the surface during annealing. The chemical compositions of sample surface axe investigated using x-ray photoelectron spectroscopy （XPS）. The results of C ls and Si 2p core-level spectra axe presented in detail to demonstrate the evaporation of Si from the wafer and the deposition of SiO2 on the sample surface during annealing.
A semi-insulating layer is obtained in n-type 4H-SiC by vanadium-ion implantation. A little higher resistivity is obtained by increasing the annealing temperature from 1450 to 1650 ℃. The resistivity at room temperat...
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A semi-insulating layer is obtained in n-type 4H-SiC by vanadium-ion implantation. A little higher resistivity is obtained by increasing the annealing temperature from 1450 to 1650 ℃. The resistivity at room temperature is as high as 7.6 ×10^6 Ω. cm. Significant redistribution of vanadium is not observed even after 1650 ℃ annealing. Temperaturedependent resistivity and optical absorption of V-implanted samples are measured. The activation energy of vanadium acceptor level is observed to be at about Ec - 1.1 eV.
A new comprehensive empirical large signal model for 4H-SiC MESFETs is proposed. An enhanced drain current model, along with an improved charge conservation capacitance model, is presented by the improvement of the ch...
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A new comprehensive empirical large signal model for 4H-SiC MESFETs is proposed. An enhanced drain current model, along with an improved charge conservation capacitance model, is presented by the improvement of the channel length modulation and the hyperbolic tangent function coefficient based on the Materka model. The Levenberg-Marquardt method is used to optimize the parameter extraction. A comparison of simulation results with experimental data is made, and good agreements of I-V curves, Pout(output power), PAE (power added efficiency), and gain at the bias of VDS=20V, IDS=80mA as well as the operational frequency of 1.8GHz are obtained.
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