The process of Ti/Al/Ti/Au ohmic contact of AlGaN/GaN HEMTs were studied systematically. After the study of annealing process, we got the ohmic contact ratio of 10-7Ω·cm2. We also analyzed the mechanism of ...
详细信息
The process of Ti/Al/Ti/Au ohmic contact of AlGaN/GaN HEMTs were studied systematically. After the study of annealing process, we got the ohmic contact ratio of 10-7Ω·cm2. We also analyzed the mechanism of ohmic contact of AlGaN/GaN HEMTs. Based on the optimization of device fabrication, we developed high performance AlGaN/GaN HEMTs. The device with 40 μm gate width has reached a maximum extrinsic transconductance of 250 mS/mm, and the current density of the device with 0.8 mm gate width is 1.07 A/mm(Ve = 0.5V) at Vds = 30 V. The output power of 0.8 mm gate width device is 32.5 dBm(1.6 W) at 8 GHz, the output power density is 2.14 W/mm and power gain 12.7 dB.
After 3 × 104 s of high-field stress, the drain current and transconductance of AlGaN/GaN HEMTs grown on sapphire are decreased by 5.2% and 7.6%, respectively. The degradation is more obvious than under high stre...
详细信息
After 3 × 104 s of high-field stress, the drain current and transconductance of AlGaN/GaN HEMTs grown on sapphire are decreased by 5.2% and 7.6%, respectively. The degradation is more obvious than under high stress bias. The reason for this is investigated and compared to the current collapse that occurs under DC sweeping. The effects of UV irradiation on the recovery of the devices are observed. UV illumination can eliminate the DC sweeping current collapse, but it cannot reverse the degradation characteristics caused by the high-field stress.
The timing characteristics of random telegraph signal (RTS) in deep submicron MOS devices are investigated, and a novel method is proposed to determine the spatial distribution of the border traps by forward and backw...
详细信息
The timing characteristics of random telegraph signal (RTS) in deep submicron MOS devices are investigated, and a novel method is proposed to determine the spatial distribution of the border traps by forward and backward RTS measurements in the non-saturation state. The measurements of a 0.18 μm × 0.15 μm nMOS device show that the two-dimension position of the trap in the oxide of a deep submicron MOS device can be precisely calculated with this method. This method can also evaluate the reliability of deep submicron MOS devices.
The DC characteristics of AlGaN/GaN HEMTs are measured in a temperature range from 25 to 200°C. On the same wafer, Schottky C-V and transmission line model measurements are carried out at different temperatures. ...
详细信息
The DC characteristics of AlGaN/GaN HEMTs are measured in a temperature range from 25 to 200°C. On the same wafer, Schottky C-V and transmission line model measurements are carried out at different temperatures. The temperature dependence of the distribution of the two-dimensional electron gas, the sheet resistance, the ohmic specific contact resistance, and the buffer leakage current are analyzed. We conclude that the reduced saturation current is mainly due to the degradation of the electron transport property. The channel leakage current arises from the gate leakage current, and the leakage of the GaN buffer layer plays a secondary role.
Semi-insulating layers could be successfully formed by vanadium ion (V+) implantation in 4H-SiC. The fabrication processes and characteristics of the implanted layer are developed in details. The profile of implantati...
详细信息
Semi-insulating layers could be successfully formed by vanadium ion (V+) implantation in 4H-SiC. The fabrication processes and characteristics of the implanted layer are developed in details. The profile of implantation depth is simulated using the Monte Carlo simulator TRIM. Resistivity measurements are performed for the semi-insulating 4H-SiC samples. The resistivity of V+-implanted layer is strongly dependent on the conduction type of initial 4H-SiC sample. The resistivity at room temperature is about 1.2 × 109-1.6 × 1010Ω·cm and 2.0 × 106-7.6 × 106Ω ·cm for p-and n-type samples, respectively.
SiGe BiCMOS technology provides us with ultrahigh speed HBTs. The transistors have characteristics of excellent linearity (IP3), low noise figure (NFmin), ultrahigh speed (f approximately equals 70 GHz). An 8-bit full...
详细信息
SiGe BiCMOS technology provides us with ultrahigh speed HBTs. The transistors have characteristics of excellent linearity (IP3), low noise figure (NFmin), ultrahigh speed (f approximately equals 70 GHz). An 8-bit fully differential comparator using SiGe BiCMOS is established. It consists of a preamplifier with wide bandwidth, an improved master latch and a slave latch. Its full-scale differential input range is 0.8 V, its differential output is 0.4 V, and the maximum clock frequency is over 10 GHz with a single 3.3 V power supply. Its input offset is about 2.5 mV and it can be used in an 8-bit two-step flash ADC.
The direct tunneling effect in SiC Schottky contacts is simulated based on electron tunneling probabilities through a triangular barrier, which are accurately solved using the one-dimensional time-independent Schr...
详细信息
The direct tunneling effect in SiC Schottky contacts is simulated based on electron tunneling probabilities through a triangular barrier, which are accurately solved using the one-dimensional time-independent Schrödinger equation. The simulation results show that the proposed method has the advantages of greater accuracy and adaptability to SiC Schottky contacts in high fields over the WKB approximation. It also can seamlessly treat thermionic emission and tunneling current.
We present a theoretical and experimental investigation of the date retention ability of EEPROM cells at a given voltage. An expression for EEPROM data retention is derived. The electrical characteristics are presente...
详细信息
We present a theoretical and experimental investigation of the date retention ability of EEPROM cells at a given voltage. An expression for EEPROM data retention is derived. The electrical characteristics are presented. The result shows that the data retention time varies linearly with the applied voltage in a log-log plot. Under the assumption that the charge loss mechanism is Fowler-Nordheim tunneling through the thin oxide, the data retention time of EEPROM cells is derived, and the experience formula is checked by experiment.
The distortion of the C-V characteristics of a SiC buried-channel MOS structure is presented. It is difficult to characterize the gate capacitance because there is a pn junction in buried-channel MOSFETs. The surface ...
详细信息
The distortion of the C-V characteristics of a SiC buried-channel MOS structure is presented. It is difficult to characterize the gate capacitance because there is a pn junction in buried-channel MOSFETs. The surface depletion region and n-side space-charge region merge when the channel is punched through. In this case, the total surface capacitance is the sum of the surface depletion region capacitance and the pn junction capacitance, and the C-V characteristics are distorted. The analytic expression of gate capacitance in the pinch-off mode is obtained by solving Poisson's equation. The C-V characteristics in the pinch-off mode are analyzed on a fundamental physical level. The gate capacitance calculated with the model agrees well with experimental results.
Vanadium ion (V+) implantation at a high energy (2100 keV) is successfully used to form semi-insulating layers in 4H-SiC. The fabrication processes and measurements of the implanted layer are reported in detail. The p...
详细信息
Vanadium ion (V+) implantation at a high energy (2100 keV) is successfully used to form semi-insulating layers in 4H-SiC. The fabrication processes and measurements of the implanted layer are reported in detail. The profile of the ion implantation is simulated with the Monte Carlo simulator TRIM. Test patterns on semi-insulating 4H-SiC samples are processed into a mesa structure, and resistivity measurements are conducted. The resistivities of V+-implanted layers are strongly dependent on the conduction type of the initial 4H-SiC samples, and they are about 1.6 × 1010 and 7.6 × 106 Ω·cm respectively for p- and n-type samples at room temperature. The resistivities of the as-implanted samples increase with increasing annealing temperature for both p- and n-type samples due to the introduction of compensating levels. However, they decrease slightly beyond 1700°C due to the diffusion of vanadium. The temperature dependent resistivity behavior in V+-implanted n-type 4H-SiC indicates an activation energy of 0.78 eV.
暂无评论