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2021 IEEE International Conference on Integrated circuits, Technologies and Applications, ICTA 2021

作者： Zheng, Xu Yu, Jie Sun, Wenxuan Lai, Jinru Dong, Danian Xing, Guozhong Xu, Xiaoxin Institute of Microelectronics Chinese Academy of Sciences Key Laboratory of Microelectronics Devices and Integrated Technology Beijing China University of Chinese Academy of Sciences China

ISBN: (纸本)9781665417471

The unpredictable soft-error is an important reliability issue hindering the application of the Resistive random-access memory (RRAM). In this paper, we investigated the influence of conductive filament (CF) morphology on the soft-error during the reprogrammable operation. Different filament morphology could be achieved by adopting different programing scheme for forming operation in the oxide RRAM with the structure of TiN/IL/TaOx /TiN. Hourglass shaped filament is more likely to be formed by using the bidirectional forming (Bi-F) scheme and shows more soft-error during the endurance measurement. The mechanism could be explained by the recombination of oxygen ions and oxygen vacancies in the active regions. This paper has guiding significance for the memory optimization and application. © 2021 IEEE.

关键词： RRAM

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β-GaO Lateral Schottky Barrier Diodes with > 10 kV Breakdown Voltage and Anode Engineering

IEEE Electron Device Letters

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IEEE Electron Device Letters 2023年第10期44卷 1684-1687页

作者： Wang, Chenlu Yan, Qinglong Zhang, Chaoqun Su, Chunxu Zhang, Kun Sun, Sihan Liu, Zhihong Zhang, Weihang Alghamdi, Sami Ghandourah, Emad Zhang, Chunfu Zhang, Jincheng Zhou, Hong Hao, Yue Xidian University Key Laboratory of Wide Band Gap Semiconductor Materials and Devices School of Microelectronics Xi'an710071 China Guangzhou Institute of Technology Xidian University Guangzhou Wide Band Gap Semiconductor Innovation Center Guangzhou510555 China King Abdulaziz University Department of Electrical and Computer Engineering Jeddah21589 Saudi Arabia

In this letter, we demonstrated β-Ga2O3 lateral Schottky barrier diodes (SBDs) with breakdown voltage (BV) over 10 kV via anode engineering techniques. Postanode deposition annealing (PAA) was implemented to enhance the Schottky barrier height (SBH) to minimize the leakage current and suppress the interface state density (Dit) by over 1 order of magnitude. It is found that the Dit was extracted to be only 3 × 1010 cm-2eV-1 at the energy level near the conduction band after the PAA treatment. Benefiting from the PAA and the coupled as well as the carefully designed dual field-plate (FP) structure, the BV of the SBD was enhanced from about 4 kV to over 10 kV while the turn-on voltage (Von) for those SBDs remained approximately at 1 V. These findings show the immense potential of anode engineered Ga2O3 diodes for future high-voltage and high-power electronic systems. © 1980-2012 IEEE.

关键词： Deposition

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The Roadmap of 2D Materials and devices Toward Chips

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Nano-Micro Letters 2024年第6期16卷 343-438页

作者： Anhan Liu Xiaowei Zhang Ziyu Liu Yuning Li Xueyang Peng Xin Li Yue Qin Chen Hu Yanqing Qiu Han Jiang Yang Wang Yifan Li Jun Tang Jun Liu Hao Guo Tao Deng Songang Peng He Tian Tian‑Ling Ren School of Integrated Circuits and Beijing National Research Center for Information Science and Technology(BNRist) Tsinghua UniversityBeijing 100049People’s Republic of China School of Microelectronics Fudan UniversityShanghai 200433People’s Republic of China State Key Laboratory of Dynamic Measurement Technology Shanxi Province Key Laboratory of Quantum Sensing and Precision MeasurementNorth University of ChinaTaiyuan 030051People’s Republic of China High‑Frequency High‑Voltage Device and Integrated Circuits R&D Center Institute of MicroelectronicsChinese Academy of SciencesBeijing 100029People’s Republic of China School of Electronic and Information Engineering Beijing Jiaotong UniversityBeijing 100044People’s Republic of China School of Integrated Circuits University of Chinese Academy of SciencesBeijing 100049People’s Republic of China IMECAS-HKUST-Joint Laboratory of Microelectronics Beijing 100029People’s Republic of China

Due to the constraints imposed by physical effects and performance degra certain limitations in sustaining the advancement of Moore’s ***-dimensional(2D)materials have emerged as highly promising candidates for the post-Moore era,offering significant potential in domains such as integrated circuits and next-generation ***,in this review,the progress of 2D semiconductors in process engineering and various electronic applications are summarized.A careful introduction of material synthesis,transistor engineering focused on device configuration,dielectric engineering,contact engineering,and material integration are given *** 2D transistors for certain electronic applications including digital and analog circuits,heterogeneous integration chips,and sensing circuits are ***,several promising applications(artificial intelligence chips and quantum chips)based on specific mechanism devices are ***,the challenges for 2D materials encountered in achieving circuit-level or system-level applications are analyzed,and potential development pathways or roadmaps are further speculated and outlooked.

关键词： Two-dimensional materials Roadmap Integrated circuits Post-Moore era

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Integrated Organic Electrochemical Transistors for Serotonin Detection and Synaptic Plasticity

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IEEE Journal of the Electron devices Society 2025年

作者： Xie, Yifan Jin, Qingqing Cheng, Miao Tian, Yue Wang, Jinyao Chu, Jingyun Liu, Changrui Li, Mengmeng Chinese Academy of Sciences State Key Laboratory of Fabrication Technologies for Integrated Circuits Beijing100029 China Chinese Academy of Sciences Institute of Microelectronics Beijing100029 China University of Chinese Academy of Sciences School of Integrated Circuits Beijing100049 China

Organic electrochemical transistors (OECTs) have gained increasing attention for their potential in neuromorphic electronics and neurotransmitter sensing, thanks to their inherent low-power operation and high sensitivity. This study introduces an integrated on-chip Ag/AgCl gate architecture for OECTs, which not only exhibits identical performance with devices using traditional external gates but also enables the integration of a uniform 3W3 transistor array. The resulting array demonstrates consistent performance across individual devices, characterized by uniform transconductance, on/off ratios, threshold voltages, and charge-carrier mobility. Notably, these OECTs function as highly sensitive biosensors for serotonin detection, achieving a detection limit of 0.5 nM. Furthermore, exposure to serotonin triggers a transition from short-term to long-term plasticity in the OECTs, mirroring the processes underlying synaptic memory formation. These findings open new avenues for the development of large-area bioelectronics and neuromorphic computing systems. © 2013 IEEE.

关键词： Integration

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Experimental Demonstration of A CT-FeFET Array with Intrinsic Long-Short-Term Plasticity for Low-Cost Trajectory Prediction

Experimental Demonstration of A CT-FeFET Array with Intrinsi...

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International Electron devices Meeting (IEDM)

作者： Chao Li Jie Yu Xumeng Zhang Zhaohao Zhang Fangduo Zhu Siyuan Ouyang Pei Chen Lingli Cheng Gaobo Xu Qingzhu Zhang Huaxiang Yin Qi Liu Ming Liu State Key Laboratory of Integrated Chips and Systems Frontier Institute of Chip and System Fudan University Shanghai China Key Laboratory of Microelectronic Devices and Integrated Technology Institute of Microelectronics Chinese Academy of Sciences Beijing China Key Laboratory of Fabrication Technologies for Integrated Circuits Chinese Academy of Sciences Beijing China

ISBN: (数字)9798350365429

ISBN: (纸本)9798350365436

Trajectory prediction is a vital function in the auto-driving field, typically achieved with a long short-term memory network. Static IMC technology accelerates the computing of long-term parameters, while the execution of short-term parameters faces great buffer overhead. Inspired by the fused long-short-term synaptic plasticity in biology, here, we proposed a dynamic IMC strategy based on a charge-trapping FeFET array with intrinsic long-short-term plasticity. The long-term weights are stored in the ferroelectric domain, while the short-term weights are in-situ dynamically operated in a charge-trapping domain, eliminating the external caching process. We further demonstrated a dynamic IMC neuromorphic system built on this array for performing trajectory prediction of moving vehicles, achieving more than 1000x and 4x improvements than GPU in power consumption and memory overhead.

关键词： Performance evaluation Power demand Neuromorphics Memory management Graphics processing units Trajectory Vehicle dynamics Synapses Long short term memory FeFETs

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Cell Structure and Process Integration of a Novel 2T0C Technology for High-Density Dram Application

Cell Structure and Process Integration of a Novel 2T0C Techn...

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China Semiconductor Technology International Conference (CSTIC)

作者： Zheng-Yong Zhu Bok-Moon Kang Jing Zhang Xin-Lv Duan Jin-Juan Xiang Guan-Hua Yang Di Geng Wang Dan Xie-Shuai Wu Ming-Xu Liu Gui-Lei Wang Chao Zhao Beijing Superstring Academy of Memory Technology Beijing China Key Laboratory of Microelectronics Devices and Integrated Technology Institute of Microelectronics Chinese Academy of Sciences Beijing China

A new DRAM 2T0C cell is introduced to resolve those special issues for traditional 2T0C DRAM. In this technology, the read transistor holds dual gates. The data is stored in one gate of read transistor, and the other gate is used to control read operation. By writing different-level voltages into storage gate, the read transistor will have different threshold voltages by using the other gate as control gate. Compared with 1T1C DRAM, read operation in this new technology is non-destructive and therefore no explicit capacitor is required. Low leakage is essential for write transistor to obtain long data retention time. A few cell structures of this new 2T0C technology are discussed for high-density DRAM application, and challenges of process integration is also analyzed.

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A DC-DC converter utilizing \beta-\text{Ga}_{2}O}_{3 Schottky barrier diode 5

A DC-DC converter utilizing \beta-\text{Ga}_{2}O}_{3 Schottk...

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5th IEEE Electron devices Technology and Manufacturing Conference, EDTM 2021

作者： Guo, Wei Jian, Guangzhong Wu, Feihong Zhou, Kai Xu, Guangwei Zhou, Xuanze He, Qiming Zhao, Xiaolong Long, Shibing School of Microelectronics University of Science and Technology of China Hefei230026 China Key Laboratory of Microelectronics Devices and Integration Technology Institute of Microelectronics of Chinese Academy of Sciences Beijing100029 China

ISBN: (纸本)9781728181769

The \beta-\text{Ga}_{2}O}_{3 Schottky barrier diode (SBD) is fabricated and actualized a breakdown voltage of 472 V. A SPICE model for \beta-\text{Ga}_{2}O}_{3 Sbd is derived from experimental results and applied to DC-DC converter circuit simulation. Then the \beta-\text{Ga}_{2}O}_{3 SBD is implemented in a DC-DC converter circuit and acquired the conversion efficiency of 94.8%, indicating the great potential of Ga2O3-based devices and circuits. © 2021 IEEE.

关键词： Schottky barrier diodes

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Microscopic mechanism of imprint in hafnium oxide-based ferroelectrics

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Nano Research 2022年第4期15卷 3667-3674页

作者： Peng Yuan Ge-Qi Mao Yan Cheng Kan-Hao Xue Yunzhe Zheng Yang Yang Pengfei Jiang Yannan Xu Yuan Wang Yuhao Wang Yaxin Ding Yuting Chen Zhiwei Dang Lu Tai Tiancheng Gong Qing Luo Xiangshui Miao Qi Liu Key Laboratory of Microelectronic Devices and Integrated Technology Institute of MicroelectronicsChinese Academy of SciencesNo.3Beitucheng West RoadBeijing 100029China University of Chinese Academy of Sciences 19 Yuquan RoadBeijing 100049China School of Integrated Circuits School of Optical and Electronic InformationHuazhong University of Science and Technology1037 Luoyu RoadWuhan 430074China Key Laboratory of Polar Materials and Devices(MOE) Department of ElectronicsEast China Normal University100 Guilin RoadShanghai 430079China Department of Mathematics and Theories Peng Cheng LaboratoryNo.2Xingke 1st StreetShenzhen 518055China

Hafnia-based ferroelectrics have greatly revived the field of ferroelectric memory(FeRAM),but certain reliability issues must be satisfactorily resolved before they can be widely applied in commercial *** particular,the imprint phenomenon severely jeopardizes the read-out reliability in hafnia-based ferroelectric capacitors,but its origin remains unclear,which hinders the development of its recovery *** this work,we have systematically investigated the imprint mechanism in TiN/Hf_(0.5)Zr_(0.5)O_(2)(HZO)/TiN ferroelectric capacitors using experiments and first-principles *** is shown that carrier injection-induced charged oxygen vacancies are at the heart of imprint in HZO,where other mechanisms such as domain pinning and dead layer are less *** imprint model based on electron de-trapping from oxygen vacancy sites has been proposed that can satisfactorily explain several experimental facts such as the strong asymmetric imprint,leakage current variation,and so *** on this model,an effective imprint recovery method has been proposed,which utilizes unipolar rather than bipolar voltage *** remarkable recovery performances demonstrate the prospect of improved device reliability in hafnia-based FeRAM devices.

关键词： hafnia-based ferroelectric imprint build-in electric field oxygen vacancy recovery

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Improved Memory Window and Retention of Silicon Channel Hf0.5Zr0.5O2 FeFET by Using SiO2/HfO2/SiO2 Gate Side Interlayer

Improved Memory Window and Retention of Silicon Channel Hf0....

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Annual International Symposium on Reliability Physics

作者： Runhao Han Jia Yang Tao Hu Mingkai Bai Yajing Ding Xianzhou Shao Saifei Dai Xiaoqing Sun Junshuai Chai Hao Xu Xiaolei Wang Wenwu Wang Tianchun Ye Chinese Academy of Sciences Key Laboratory of Fabrication Technologies for Integrated Circuits Beijing Chinese Academy of Sciences Institute of Microelectronics Beijing China School of Integrated Circuits University of Chinese Academy of Sciences Beijing China

ISBN: (数字)9798331504779

ISBN: (纸本)9798331504786

We demonstrate a Si-channel Hf 0 . 5 Zr 0 . 5 O 2 FeFET that achieves a record-high memory window (MW) of up to 19.4 V, together with improved data retention. This advancement is realized by inserting the SiO 2 /HfO 2 /SiO 2 gate interlayer between the metal gate and the ferroelectric Hf 0 . 5 Zr 0 . 5 O 2 layer. The gate interlayer effectively retains the charges injected from the metal gate. The influence of SiO 2 thickness on the reliability was investigated. Although thicker SiO 2 layer enhance the memory window, its endurance is poor. The data retention improves with increasing SiO 2 layer thickness. Furthermore, the charge trapping behaviors of gate-injected electrons and holes are asymmetric. This work provides new insights into the gate-injected charges and data retention in the FeFETs with gate interlayer.

关键词： Zirconium Hafnium Logic gates Charge carrier processes Hafnium oxide Silicon Reliability FeFETs Physics

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Comparative Study of TID Irradiation Effect on SiC Planar and Trench MOSFET 21

Comparative Study of TID Irradiation Effect on SiC Planar an...

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21st China International Forum on Solid State Lighting and 10th International Forum on Wide Bandgap Semiconductors, SSLCHINA: IFWS 2024

作者： Fu, Zhen Shen, Zhanwei Tang, Xuan Huang, Yu Xu, Jinyi Huang, Kaige Zhang, Quan Chen, Yanning Xiao, Chao Huang, Kai Yue, Shizhong Wang, Zhijie Zhang, Feng the Beijing Smartchip Microelectronics Technology Co. Ltd Beijing102200 China the Laboratory of Solid-State Optoelectronics Information Technology Key Laboratory of Semiconductor Material Sciences Beijing Key Laboratory of Low Dimensional Semiconductor Materials and Devices Institute of Semiconductors Chinese Academy of Sciences Beijing100083 China the Center of Materials Science and Optoelectronics Engineering University of Chinese Academy of Sciences Beijing100049 China

ISBN: (纸本)9798331541149

In this work, the mechanisms of total ionizing dose irradiation (TID) induced charge collections are analyzed and compared between SiC planar and trench gate metal-oxide-semiconductor field effect transistor (DMOSFET and UMOSFET). The threshold shift and the blocking capability of the post-irradiated devices are strongly associated with degradation of the MOS channel regions. Furthermore, SiC UMOSFET with low dose irradiation of 100 Krad(Si) exhibits a higher degree of degradation of electrical characteristics than that of the DMOSFET with irradiation of 300 Krad(Si). For comparison, the fabricated DMOSFET shows negligible change in gate leakage current and stable blocking capability after 100 Krad(Si) irradiation. Also, the edge-corner topography of gate poly-Si in both of SiC MOSFETs is found to have influence on the formation of latent gate damage induced by TID irradiation. For purpose of deep understanding of these results, the charge interaction on both sides of the gate oxide is clarified by dynamic capacitance comparisons obtained by experimental and numerical methods. SiC UMOSFET with a large portion of the trench surrounded by p-type regions shows greater capacitance shift than the DMOSFET. It is indicated that the ratio of gate/p-type-regions overlap in one cell may have effects on the charge collection of post-irradiated devices. These results will provide meaningful guidance for the design and fabrication of a radiation tolerant SiC MOSFETs. ©2024 IEEE.

关键词： MOSFET devices

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