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IEEE International Conference on Artificial Intelligence circuits and Systems (AICAS)

作者： Guang Chen Jian Cao Shuo Feng Zilin Wang Yi Zhong Qibin Li Xiongbo Zhao Xing Zhang Yuan Wang School of Software and Microelectronics Peking University Beijing China Key Laboratory of Microelectronic Devices and Circuits (MoE) MPW Center Peking University Beijing China School of Integrated Circuits Peking University Beijing China Beijing Aerospace Automatic Control Institute Beijing China

ISBN: (数字)9798350383638

ISBN: (纸本)9798350383645

Spiking neural network (SNN), a bio-inspired neuron network, utilizes a learning rule named spike-timing-dependent plasticity (STDP) to achieve high-performance unsupervised learning. However, it may suffer from catastrophic forgetting when the distribution of new data significantly differs from that of old data. To address this issue, an incremental learning implementation for ship classification is presented in this paper. We develop an incremental learning algorithm based on STDP and corresponding platform. A competitive SNN is built into our algorithm, and add-STDP is utilized to update the weights of network for efficient learning. To enhance learning performance, we incorporate weight decay. And to avoid catastrophic forgetting, we incorporate data replay. The corresponding learning platform consists of the FPGA Zynq 7100 and the STDP neuromorphic prototype chip, and our algorithm is executed on the chip. We evaluate the ship classification task on our platform, which demonstrates the superior potential of our on-chip implementation for incremental learning.

关键词： Incremental learning Neuromorphics Neurons Prototypes Spiking neural networks Classification algorithms System-on-chip

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Interface Treatment of Epitaxial SI FINFET Channel in Replace Metal Gate with Simultaneously Performance Improvement and Leakage Reduction

Interface Treatment of Epitaxial SI FINFET Channel in Replac...

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China Semiconductor Technology International Conference (CSTIC)

作者： Renjie Jiang Lei Cao Wenjuan Xiong Jiaxin Yao Peng Wang Yadong Zhang Guanqiao Sang Lianlian Li Meihe Zhang Huaxiang Yin Jun Luo Integrated Circuit Advanced Process R&D Center Institute of Microelectronics of the Chinese Academy of Sciences Beijing China School of Integrated Circuits University of Chinese Academy of Sciences Beijing China State key Laboratory of Fabrication Technologies for Integrated Circuits Institute of Microelectronics of the Chinese Academy of Sciences Beijing China

ISBN: (数字)9798350362190

ISBN: (纸本)9798350362206

Channel surface defects are an important factor causing poor device interface characteristics and deterioration of sub-threshold characteristics. In order to reduce the interface trap density (Dit) of epitaxial silicon FinFET devices and improve device performance, an in-situ steam generation (ISSG) oxidation and diluted hydrofluoric acid (DHF) cleaning method was proposed to repair the damaged channel surface and reduce the interface defect charge (Q it ) replace metal gate (RMG) module. The thickness of Fin top narrows, and Fin's steepness decreases, after interfacial ISSG oxidation treatment. The electrical results demonstrate that the SS for the NFET with interface treatment are decreased from 74.2 mv/dec to 70.97 mV/dec due to the interface improvement. At the same time, the leakage current reduced from 1.0E-2 μA to 5.67E-4 μA, and the Ion is increased by 16.89% compared with that of conventional FinFET without interface treatment.

关键词： Metals DH-HEMTs Maintenance engineering Logic gates FinFETs Oxidation Silicon

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A Monolithic GaN LDO Based on 12 V/0.5 μm GaN-on-Si Power Technology Achieving 20 ns Settling Time and 22 MHz UGF 16

A Monolithic GaN LDO Based on 12 V/0.5 μm GaN-on-Si Power T...

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16th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2022

作者： Wang, Peng Jiang, Yi-Zhou Liu, Dong-Sheng Zhang, You Li, Wen-Hong Huang, Wei Xiao, Zhi-Qiang Qiu, Yi-Wu Zhou, Xin-Jie Yang, Hong-Qiang Zhang, Wei Fudan University State Key Laboratory of Asic and System Shanghai Institute of Intelligent Electronics & Systems School of Microelectronics Shanghai200433 China Wuxi Microelectronics Scientific and Research Center Wuxi214035 China University of Electronic Science and Technology of China The State Key Laboratory of Electronic Thin Films and Integrated Devices Chengdu610054 China

ISBN: (数字)9781665469067

ISBN: (纸本)9781665469067

In this paper, a fast transient response capacitor-less gallium nitride (GaN)-based LDO on the GaN smart power technology platform for GaN integrated power regulation application is first proposed. A proposed GaN error amplifier (EA) with bootstrapping technology can effectively boost the gain to 45 dB. By employing the EA and a regulator enhancement-mode HEMT, the LDO is able to achieve a 22 MHz unit gain frequency with a load capacitor and current ranging from 0 pF to10 pF and 250 μA to 100mA, respectively. And the short settling time (20 ns) for 50-100 mA load change in 10 ns edge-time without load capacitor manifests superior high-frequency performance compared to silicon-based LDO. The circuit further promotes the development of an all-GaN solution compact power management system with improved reliability and performance. © 2022 IEEE.

关键词： Gallium nitride

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CMOS-compatible wafer-scale Si subulate array for superb switching uniformity of RRAM with localized nanofilaments

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Science China Materials 2022年第6期65卷 1623-1630页

作者： Ying Zhang Xiaolong Zhao Xiaolan Ma Yu Liu Xuanze Zhou Meiyun Zhang Guangwei Xu Shibing Long Key Laboratory of Microelectronic Devices&Integration Technology Institute of MicroelectronicsChinese Academy of SciencesBeijing 100029China School of Microelectronics University of Science and Technology of ChinaHefei 230026China University of Chinese Academy of Sciences Beijing 100049China

Resistive switching random access memory(RRAM)is one of the most promising candidates with highdensity three-dimensional integration characteristics for nextgeneration nonvolatile memory ***,the poor uniformity issue caused by the stochastic property of the conductive filament(CF)impedes the large-scale manufacture of RRAM *** array has been introduced into the RRAM to minimize the CF randomness,but the methods are cumbersome,expensive,or resolution-limited for large-scale *** this work,Si subulate array(SSA)substrates with different curvature radii prepared by a wafer-scale and nanoscale-controllable method are introduced for RRAM *** SSA structure,which induces a quasi-single CF or a few CFs formed in the tip region(TR)of the device as evidenced by the high-resolution transmission electron microscopy and energy dispersive spectroscopy characterization,dramatically improves the cycle-to-cycle and device-to-device *** the curvature radius of the TR significantly improves the device performance,including switching voltages,high/low resistance states,and retention *** improved uniformity can be attributed to the enhanced local electric field in the *** proposed SSA provides a low-cost,uniform,CMOS-compatible,and nanoscale-controllable optimization strategy for the largescale integration of highly uniform RRAM devices.

关键词： resistive switching memristor RRAM Si subulate array enhancement of electric field

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A Sige Channel Gate-All-Around Transistor Fabricated Using Novel Cyclic Self-Limiting Wet Etching Combined with SI Removal Process

A Sige Channel Gate-All-Around Transistor Fabricated Using N...

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China Semiconductor Technology International Conference (CSTIC)

作者： KaiMin Feng HaoYan Liu HuaiZhi Luo Xi Zhang YongLiang Li Key Laboratory of Fabrication Technologies for Integrated Circuits Chinese Academy of Sciences Beijing China Institute of Microelectronics Chinese Academy of Sciences Beijing China School of Integrated Circuits University of Chinese Academy of Sciences Beijing China

ISBN: (数字)9798331513351

ISBN: (纸本)9798331513368

In this work, a novel SiGe channel gate-all-around (GAA) transistor using a cyclic self-limiting wet etching process combined with Si removal process after dummy gate removal in the mainstream FinFET process is demonstrated in detail. The width of SiGe channel is narrowed from 20 nm to 6.5 nm and its mole fraction of Ge of SiGe channel can be increased from 31.8% to ~40%. Meanwhile, I DS of 382 μA/μm is obtained at V DS = V GS = -0.8V, with I ON /I OFF ratio of ~5.5e5 and SS of 76 mV/dec. These results prove that this novel process provides a potential solution to prepare the SiGe channel GAA transistor.

关键词： Integrated circuits Wet etching Gallium arsenide Logic gates FinFETs Germanium Silicon Transistors Silicon germanium

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Millimeter-Wave AlGaN/GaN HEMTs/Si Operated on 12V for 5G RF Handset Applications 16

Millimeter-Wave AlGaN/GaN HEMTs/Si Operated on 12V for 5G RF...

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16th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2022

作者： Liu, Dong-Sheng Wang, Peng Jiang, Yi-Zhou Huang, Wei Xiao, Zhi-Qiang Yang, Hong-Qiang Zhang, Wei. Fudan University State Key Laboratory of Asic and System Shanghai Institute of Intelligent Electronics & Systems School of Microelectronics Shanghai200433 China Wuxi Microelectronics Scientific and Research Center Wuxi214035 China University of Electronic Science and Technology of China The State Key Laboratory of Electronic Thin Films and Integrated Devices Chengdu610054 China

ISBN: (数字)9781665469067

ISBN: (纸本)9781665469067

In this paper, a RF AlGaN/GaN high electron mobility transistor (HEMT) based on low voltage application of 5G RF handset, firstly fabricated on high-resistive silicon substrate is introduced, which uses Ni/Au as T-shaped gate structure and double-layer silicide as surface medium. The maximum output current density of the device is 1.07 A/mm at Vds = 12 V and Vgs = 2 V. fT = 27.8 GHz and BV (the breakdown voltage) = 35 V/μm are obtained for the 180-nm gate-length device with 1-μm source-to-gate spacing. © 2022 IEEE.

关键词： Silicides

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An Aging Small-signal Modeling Method of Microwave Transistors Using GA-ELM Neural Network

An Aging Small-signal Modeling Method of Microwave Transisto...

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Electronics Design Automation (ISEDA), International Symposium of

作者： Lin Cheng Hongliang Lu Xiuxiu Guo Silu Yan Wei Cheng Yuming Zhang School of Microelectronics Xidian University Xi'an China Science and Technology on Monolithic Integrated Circuits and Modules Laboratory Nanjing Electronic Devices Institute Nanjing China

In this paper, an aging small-signal S-parameters modeling method for microwave transistors is explored using a genetic algorithm (GA) to optimize the Extreme Learning Machine (ELM) neural network. A dual GA-ELM neural network architecture was used to simulate the fresh S-parameters of InP heterojunction bipolar transistor (HBT) devices and the degradation of S-parameters after accelerated aging, respectively. Good agreement was achieved between measured and predicted results of the fresh and aging S-parameters within a frequency range of 0.1 to 40 GHz.

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A Novel Load-Si-Cut SOI Nanosheets Transistors with Ultrathin SiGe Cladded Si Channel Structure to Suppress Leakage and Enhance Driven Current

A Novel Load-Si-Cut SOI Nanosheets Transistors with Ultrathi...

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China Semiconductor Technology International Conference (CSTIC)

作者： Longyu Sun Yu Zhou Haoyan Liu Yongliang Li Key Laboratory of Fabrication Technologies for Integrated Circuits Chinese Academy of Sciences Beijing China Chinese Academy of Sciences Institute of Microelectronics Beijing China School of Integrated Circuits University of Chinese Academy of Sciences Beijing China

ISBN: (数字)9798331513351

ISBN: (纸本)9798331513368

In this article, we propose a novel load-Si-cut silicon-on-insulator (SOI) nanosheets transistors (NSFETs) with ultrathin SiGe cladded Si channel structure, named as LSC-SOI NSFETs, improving the drive current and suppressing leakage issues in the conventional SOI (C-SOI) NSFETs. The electrical characteristics of PMOS device, inverters and ring oscillators (RO) of C-SOI and LSC-SOI NSFETs were investigated using 3D technology computer-aided design (TCAD) simulation.

关键词： Ring oscillators Design automation Three-dimensional displays Silicon-on-insulator Logic gates Silicon Inverters Transistors Silicon germanium MOS devices

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Gesture recognition algorithm combining ResNet and ShuffleNet

Gesture recognition algorithm combining ResNet and ShuffleNe...

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2021 International Conference on Internet of Things and Machine Learning, IoTML 2021

作者： Xie, Zhengjiang Lou, Li Jia, Kunpeng Jiao, Binbin School of Computing Xi'an Shiyou University Xi'an Shanxi710065 China Key Laboratory of Microelectronic Devices and Integration Technology Institute of Microelectronics Chinese Academy of Sciences Beijing100029 China

ISBN: (数字)9781510653269

ISBN: (纸本)9781510653252

Gesture is a form of non-verbal communication and has many applications, such as sign language communication between deaf and dumb people, robot control, human-computer interaction and medical applications. The commonly used acquisition equipment in gesture recognition is the visible light camera, but illumination has a great impact on the accuracy of the collected data classification processing. The whole project designed a complete end-to-end edge computing system design and deployment, the system can achieve from gesture image acquisition to gesture recognition. A dataset of 3600 thermal images was created, and each gesture had 1200 thermal images with only 4∗4 resolution. These images were upsampled by bilinear interpolation and fed into a new lightweight deep learning model combining deep residual learning with ShuffleNet V2 for gesture classification. The system achieved 98.63% accuracy on the test data set. Another advantage is that it is based on thermal imaging, so the accuracy is not affected by background lighting conditions. © SPIE.

关键词： Deep learning

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Comparative Study on Degradation of the TFET and MOSFET 16

Comparative Study on Degradation of the TFET and MOSFET

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16th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2022

作者： Sun, Jiale Zhang, Yuming Lu, Hongliang Lyu, Zhijun Zhu, Yi Pan, Yuche Xidian University The Key Laboratory of Wide Band-Gap Semiconductor Materials and Devices Xi'an710071 China Institute of Microelectronics Technology The Department of Integrated Circuit Design Xi'an710004 China

ISBN: (数字)9781665469067

ISBN: (纸本)9781665469067

This paper compares the characteristics of MOSFET and TFET devices fabricated under the same process conditions. From the experimental results, it can be seen that after a period of degradation, the interface state density of the device increases, and the on-state current has a small increase, but the off state current of the TFET has the degradation obviously. The subthreshold swing also increases significantly with the device interface state degradation. The increase of off-state current and the degradation of subthreshold swing are extremely unfavorable for the application of TFET, and optimization is required to prevent the problems such as device failure. © 2022 IEEE.

关键词： Interface states

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