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IEEE Electron devices Technology and Manufacturing Conference (EDTM)

作者： Xinpei Jia Tao Hu Mingkai Bai Xiaoqing Sun Junshuai Chai Hao Xu Xiaolei Wang Wenwu Wang Tianchun Ye Institute of Microelectronics Chinese Academy of Sciences Beijing China Key Laboratory of Fabrication Technologies for Integrated Circuits Chinese Academy of Sciences Beijing China School of Integrated Circuits University of Chinese Academy of Sciences Beijing China

ISBN: (数字)9798331504168

ISBN: (纸本)9798331504175

In this work, we investigate the recombination charge during endurance cycles in Si ferroelectric field-effect transistor (FeFET) featuring Hf 0.5 Zr 0.5 O 2 /SiO 2 gate stacks, utilizing split $I-V$ measurements. Our findings indicate that when the memory window (MW) is reduced to 25% of its maximum value, the recombination charge during the fatigue process remains below approximately 10 6 μC/cm 2 across various pulse conditions. By analyzing the recombination charge per cycle, this work provides a prediction method for the endurance characteristics of the FeFET.

关键词： Pulse measurements Prediction methods Logic gates Fatigue Silicon Manufacturing Transistors FeFETs Charge measurement

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A Monolithic GaN LDO Based on 12 V/0.5 μm GaN-on-Si Power Technology Achieving 20 ns Settling Time and 22 MHz UGF 16

A Monolithic GaN LDO Based on 12 V/0.5 μm GaN-on-Si Power T...

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16th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2022

作者： Wang, Peng Jiang, Yi-Zhou Liu, Dong-Sheng Zhang, You Li, Wen-Hong Huang, Wei Xiao, Zhi-Qiang Qiu, Yi-Wu Zhou, Xin-Jie Yang, Hong-Qiang Zhang, Wei Fudan University State Key Laboratory of Asic and System Shanghai Institute of Intelligent Electronics & Systems School of Microelectronics Shanghai200433 China Wuxi Microelectronics Scientific and Research Center Wuxi214035 China University of Electronic Science and Technology of China The State Key Laboratory of Electronic Thin Films and Integrated Devices Chengdu610054 China

ISBN: (数字)9781665469067

ISBN: (纸本)9781665469067

In this paper, a fast transient response capacitor-less gallium nitride (GaN)-based LDO on the GaN smart power technology platform for GaN integrated power regulation application is first proposed. A proposed GaN error amplifier (EA) with bootstrapping technology can effectively boost the gain to 45 dB. By employing the EA and a regulator enhancement-mode HEMT, the LDO is able to achieve a 22 MHz unit gain frequency with a load capacitor and current ranging from 0 pF to10 pF and 250 μA to 100mA, respectively. And the short settling time (20 ns) for 50-100 mA load change in 10 ns edge-time without load capacitor manifests superior high-frequency performance compared to silicon-based LDO. The circuit further promotes the development of an all-GaN solution compact power management system with improved reliability and performance. © 2022 IEEE.

关键词： Gallium nitride

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CMOS-compatible wafer-scale Si subulate array for superb switching uniformity of RRAM with localized nanofilaments

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Science China Materials 2022年第6期65卷 1623-1630页

作者： Ying Zhang Xiaolong Zhao Xiaolan Ma Yu Liu Xuanze Zhou Meiyun Zhang Guangwei Xu Shibing Long Key Laboratory of Microelectronic Devices&Integration Technology Institute of MicroelectronicsChinese Academy of SciencesBeijing 100029China School of Microelectronics University of Science and Technology of ChinaHefei 230026China University of Chinese Academy of Sciences Beijing 100049China

Resistive switching random access memory(RRAM)is one of the most promising candidates with highdensity three-dimensional integration characteristics for nextgeneration nonvolatile memory ***,the poor uniformity issue caused by the stochastic property of the conductive filament(CF)impedes the large-scale manufacture of RRAM *** array has been introduced into the RRAM to minimize the CF randomness,but the methods are cumbersome,expensive,or resolution-limited for large-scale *** this work,Si subulate array(SSA)substrates with different curvature radii prepared by a wafer-scale and nanoscale-controllable method are introduced for RRAM *** SSA structure,which induces a quasi-single CF or a few CFs formed in the tip region(TR)of the device as evidenced by the high-resolution transmission electron microscopy and energy dispersive spectroscopy characterization,dramatically improves the cycle-to-cycle and device-to-device *** the curvature radius of the TR significantly improves the device performance,including switching voltages,high/low resistance states,and retention *** improved uniformity can be attributed to the enhanced local electric field in the *** proposed SSA provides a low-cost,uniform,CMOS-compatible,and nanoscale-controllable optimization strategy for the largescale integration of highly uniform RRAM devices.

关键词： resistive switching memristor RRAM Si subulate array enhancement of electric field

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Impact of Titanium Nitride (TiN) Thickness Uniformity on the Reliability of n-FinFETs: A Comparative Study of ALD and PVD TiN Techniques

Impact of Titanium Nitride (TiN) Thickness Uniformity on the...

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IEEE Electron devices Technology and Manufacturing Conference (EDTM)

作者： Mingyang Sun Yunfei Shi Hong Yang Qianqian Liu Qingzhu Zhang Tao Yang Junfeng Li Huaxiang Yin Xiaolei Wang Jun Luo Wenwu Wang Key Laboratory of Fabrication Technologies for Integrated Circuits Chinese Academy of Sciences Beijing China Institute of Microelectronics Chinese Academy of Sciences Beijing China The School of Integrated Circuits University of Chinese Academy of Sciences Beijing China

ISBN: (数字)9798331504168

ISBN: (纸本)9798331504175

To study the thickness uniformity of TiN in FinFETs, the electrical characteristics and reliability of n-FinFETs with ALD TiN and PVD TiN as barrier layer are investigated. Despite almost similar threshold voltages ( $\sim 24 \text{mV}$ ), PVD TiN-based devices exhibit poorer BTI and HCD reliability (11 % and 24 %). TCAD simulation shows that the thick-TiN in top-Fin with lower workfunction (WF) induces the large electrical field. Therefore, initial threshold voltage and reliability of n-FinFET is sensitive to the thickness variation of TiN barrier layer.

关键词： Degradation Performance evaluation Transmission electron microscopy Microscopy Tin Titanium nitride Threshold voltage Reliability Electric fields Stress

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Millimeter-Wave AlGaN/GaN HEMTs/Si Operated on 12V for 5G RF Handset Applications 16

Millimeter-Wave AlGaN/GaN HEMTs/Si Operated on 12V for 5G RF...

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16th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2022

作者： Liu, Dong-Sheng Wang, Peng Jiang, Yi-Zhou Huang, Wei Xiao, Zhi-Qiang Yang, Hong-Qiang Zhang, Wei. Fudan University State Key Laboratory of Asic and System Shanghai Institute of Intelligent Electronics & Systems School of Microelectronics Shanghai200433 China Wuxi Microelectronics Scientific and Research Center Wuxi214035 China University of Electronic Science and Technology of China The State Key Laboratory of Electronic Thin Films and Integrated Devices Chengdu610054 China

ISBN: (数字)9781665469067

ISBN: (纸本)9781665469067

In this paper, a RF AlGaN/GaN high electron mobility transistor (HEMT) based on low voltage application of 5G RF handset, firstly fabricated on high-resistive silicon substrate is introduced, which uses Ni/Au as T-shaped gate structure and double-layer silicide as surface medium. The maximum output current density of the device is 1.07 A/mm at Vds = 12 V and Vgs = 2 V. fT = 27.8 GHz and BV (the breakdown voltage) = 35 V/μm are obtained for the 180-nm gate-length device with 1-μm source-to-gate spacing. © 2022 IEEE.

关键词： Silicides

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A Sige Channel Gate-All-Around Transistor Fabricated Using Novel Cyclic Self-Limiting Wet Etching Combined with SI Removal Process

A Sige Channel Gate-All-Around Transistor Fabricated Using N...

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China Semiconductor Technology International Conference (CSTIC)

作者： KaiMin Feng HaoYan Liu HuaiZhi Luo Xi Zhang YongLiang Li Key Laboratory of Fabrication Technologies for Integrated Circuits Chinese Academy of Sciences Beijing China Institute of Microelectronics Chinese Academy of Sciences Beijing China School of Integrated Circuits University of Chinese Academy of Sciences Beijing China

ISBN: (数字)9798331513351

ISBN: (纸本)9798331513368

In this work, a novel SiGe channel gate-all-around (GAA) transistor using a cyclic self-limiting wet etching process combined with Si removal process after dummy gate removal in the mainstream FinFET process is demonstrated in detail. The width of SiGe channel is narrowed from 20 nm to 6.5 nm and its mole fraction of Ge of SiGe channel can be increased from 31.8% to ~40%. Meanwhile, I DS of 382 μA/μm is obtained at V DS = V GS = -0.8V, with I ON /I OFF ratio of ~5.5e5 and SS of 76 mV/dec. These results prove that this novel process provides a potential solution to prepare the SiGe channel GAA transistor.

关键词： Integrated circuits Wet etching Gallium arsenide Logic gates FinFETs Germanium Silicon Transistors Silicon germanium

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A Novel Load-Si-Cut SOI Nanosheets Transistors with Ultrathin SiGe Cladded Si Channel Structure to Suppress Leakage and Enhance Driven Current

A Novel Load-Si-Cut SOI Nanosheets Transistors with Ultrathi...

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China Semiconductor Technology International Conference (CSTIC)

作者： Longyu Sun Yu Zhou Haoyan Liu Yongliang Li Key Laboratory of Fabrication Technologies for Integrated Circuits Chinese Academy of Sciences Beijing China Chinese Academy of Sciences Institute of Microelectronics Beijing China School of Integrated Circuits University of Chinese Academy of Sciences Beijing China

ISBN: (数字)9798331513351

ISBN: (纸本)9798331513368

In this article, we propose a novel load-Si-cut silicon-on-insulator (SOI) nanosheets transistors (NSFETs) with ultrathin SiGe cladded Si channel structure, named as LSC-SOI NSFETs, improving the drive current and suppressing leakage issues in the conventional SOI (C-SOI) NSFETs. The electrical characteristics of PMOS device, inverters and ring oscillators (RO) of C-SOI and LSC-SOI NSFETs were investigated using 3D technology computer-aided design (TCAD) simulation.

关键词： Ring oscillators Design automation Three-dimensional displays Silicon-on-insulator Logic gates Silicon Inverters Transistors Silicon germanium MOS devices

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An Aging Small-signal Modeling Method of Microwave Transistors Using GA-ELM Neural Network

An Aging Small-signal Modeling Method of Microwave Transisto...

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Electronics Design Automation (ISEDA), International Symposium of

作者： Lin Cheng Hongliang Lu Xiuxiu Guo Silu Yan Wei Cheng Yuming Zhang School of Microelectronics Xidian University Xi'an China Science and Technology on Monolithic Integrated Circuits and Modules Laboratory Nanjing Electronic Devices Institute Nanjing China

In this paper, an aging small-signal S-parameters modeling method for microwave transistors is explored using a genetic algorithm (GA) to optimize the Extreme Learning Machine (ELM) neural network. A dual GA-ELM neural network architecture was used to simulate the fresh S-parameters of InP heterojunction bipolar transistor (HBT) devices and the degradation of S-parameters after accelerated aging, respectively. Good agreement was achieved between measured and predicted results of the fresh and aging S-parameters within a frequency range of 0.1 to 40 GHz.

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Gesture recognition algorithm combining ResNet and ShuffleNet

Gesture recognition algorithm combining ResNet and ShuffleNe...

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2021 International Conference on Internet of Things and Machine Learning, IoTML 2021

作者： Xie, Zhengjiang Lou, Li Jia, Kunpeng Jiao, Binbin School of Computing Xi'an Shiyou University Xi'an Shanxi710065 China Key Laboratory of Microelectronic Devices and Integration Technology Institute of Microelectronics Chinese Academy of Sciences Beijing100029 China

ISBN: (数字)9781510653269

ISBN: (纸本)9781510653252

Gesture is a form of non-verbal communication and has many applications, such as sign language communication between deaf and dumb people, robot control, human-computer interaction and medical applications. The commonly used acquisition equipment in gesture recognition is the visible light camera, but illumination has a great impact on the accuracy of the collected data classification processing. The whole project designed a complete end-to-end edge computing system design and deployment, the system can achieve from gesture image acquisition to gesture recognition. A dataset of 3600 thermal images was created, and each gesture had 1200 thermal images with only 4∗4 resolution. These images were upsampled by bilinear interpolation and fed into a new lightweight deep learning model combining deep residual learning with ShuffleNet V2 for gesture classification. The system achieved 98.63% accuracy on the test data set. Another advantage is that it is based on thermal imaging, so the accuracy is not affected by background lighting conditions. © SPIE.

关键词： Deep learning

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Effect of Top Al2O3 Interlayer Thickness on the Memory Window of Fefets with TiN/Al2O3/Hf0.5Zr0.5O2 /SiOx /Si (MIFIS) Gate Structure

Effect of Top Al2O3 Interlayer Thickness on the Memory Windo...

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IEEE Electron devices Technology and Manufacturing Conference (EDTM)

作者： Tao Hu Runhao Han Xinpei Jia Jia Yang Zeqi Chen Xiaoqing Sun Junshuai Chai Hao Xu Xiaolei Wang Wenwu Wang Tianchun Ye Chinese Academy of Sciences Institute of Microelectronics Beijing China Key Laboratory of Fabrication Technologies for Integrated Circuits Chinese Academy of Sciences Beijing China School of Integrated Circuits University of Chinese Academy of Sciences Beijing China

ISBN: (数字)9798331504168

ISBN: (纸本)9798331504175

In this work, we investigate the effect of top $\text{Al}_{2} \mathrm{O}_{3}$ interlayer thickness on the memory window (MW) of Si channel ferroelectric field-effect transistors (Si-FeFETs) with $\text{TiN} / \text{Al}_{2} \mathrm{O}_{3} / \text{Hf}_{0.5} \text{Zr}_{0.5} \mathrm{O}_{2} / \text{SiO}_{x} / \text{Si}$ (MIFIS) gate structure. We find that the MW first increases and then remains almost constant with the increasing thickness of the top $\text{Al}_{2} \mathrm{O}_{3}$ interlayer. This phenomenon is attributed to the smaller electric field of the ferroelectric $\text{Hf}_{0.5} \text{Zr}_{0.5} \mathrm{O}_{2}$ in the MIFIS structure with a thicker top $\text{Al}_{2} \mathrm{O}_{3}$ interlayer after a program operation, which makes the charges injected from the metal gate trapped at the top $\text{Al}_{2} \mathrm{O}_{3} / \text{Hf}_{0.5} \text{Zr}_{0.5} \mathrm{O}_{2}$ interface cannot remain.

关键词： Metals Logic gates Silicon Manufacturing Transistors Electric fields FeFETs Aluminum oxide

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