检索结果-内蒙古大学图书馆

International Conference on ASIC

作者： Hongli Tian Xiaodi Xing Jian Zhang Shaodi Wang Yuan Wang Key Laboratory of Microelectronics Devices and Circuits (MoE) MPW Center School of Integrated Circuits Peking University Beijing Zhicun (Witmem) Technology Co. Ltd Beijing Advanced Innovation Center for Integrated Circuits Beijing China

This paper designs and implements a dedicated operator called FUSE, which implements the function of image fusion in any channel and is applied to the noise reduction and super-resolution neural network designed by Witmem. The FUSE operator we designed uses 32 parallel pipeline calculations, which are internally divided into two clock domains based on the proportion of input and output data volume. We design an algorithm to search for weight address index, making the FUSE operator applicable to images of any size. Under the 28 nm standard CMOS technology, We propose the architecture of the operator and implement the hardware design. FUSE’s area is 236460.2 μm 2 , interface frequency is 1GHz, internal working frequency is 500MHz, and the throughput is 13.7GOPS when image channel is 3.

关键词：

来源：评论

学校读者我要写书评

暂无评论

Investigation of the Channel Width Dependence of IGZO TFT by Experiment and TCAD Simulation

Investigation of the Channel Width Dependence of IGZO TFT by...

引用

International Conference on Solid-State and Integrated Circuit Technology

作者： Yanyu Yang Yupeng Lu Shuang Liu Renjie Jiang Jie Luo Yunjiao Bao Peng Wang Gaobo Xu Huaxiang Yin Key Laboratory of Fabrication Technologies for Integrated Circuits Chinese Academy of Sciences Beijing Institute of Microelectronics Chinese Academy of Sciences Beijing China School of Integrated Circuits University of Chinese Academy of Sciences Beijing China

ISBN: (数字)9798350361834

ISBN: (纸本)9798350361841

In this study a inverted stagger IGZO TFTs with 350nm/250nm/100nm/50nm channel width was realized by dry etching during an active layer pattern. A severe degradation was observed with threshold voltage shift positively, SS enlarge, and mobility degradation when channel width was down to 50nm. Assisted by TCAD simulation and previous report, we confirm this degradation is attributed to insufficient reacted methyl ion and by-product absorbed on channel sidewall from the dry etching process. The methyl ion acts as negative interface trap and induces depletion region in the channel margin. This degradation effect is particularly severe when the channel width is below 100 nm.

关键词： Degradation Integrated circuit technology Fabrication Dry etching Ions Threshold voltage

来源：评论

学校读者我要写书评

暂无评论

71 GHz-fmax β-Ga2O3-on-SiC RF Power MOSFETs with Record Pout=3.1 W/mm and PAE=50.8% at 2 GHz, Pout= 2.3 W/mm at 4 GHz, and Low Microwave Noise Figure

71 GHz-fmax β-Ga2O3-on-SiC RF Power MOSFETs with Record Pou...

引用

2024 IEEE Symposium on VLSI Technology and circuits, VLSI Technology and circuits 2024

作者： Zhou, Min Zhou, Hong Mengwei, S. Gao, Guangjie Chen, Xiaojin Zhu, Xiaoxiao Dang, Kui Peijun, M. Xiaohua, M. Zheng, Xuefeng Liu, Zhihong Zhang, Jincheng Zhang, Yuhao Hao, Yue Key Laboratory of Wide Band Gap Semiconductor Materials and Devices School of Microelectronics Guangzhou Institute of Technology Xidian University Xi'an710071 China Shanghai Jiao Tong University Department of Electronic Engineering Shanghai200240 China Center for Power Electronics Systems Virginia Tech Blacksburg24060 United States

ISBN: (纸本)9798350361469

In this work, we demonstrate heavily-doped (8× 1018cm-3) and gate-recessed β-Ga2O3 RF power MOSFETs integrated on a high thermal conductivity SiC substrate to minimize self-heating effect (SHE), high on-resistance (Ron) and short-channel effect (SCE). As a result, β-Ga2O3-on-SiC RF power FETs achieve a record maximum oscillation frequency (fmax) of 71 GHz, output power density (Pout) of 3.1 W/mm and power added efficiency (PAE) of 50.8% at frequency (f) of 2 GHz and Pout=2.3 W/mm at f=4 GHz. In addition, this work for the first time studies the microwave noise performance of the β-Ga2O3 RF MOSFET at f range of 2-18 GHz with low minimum-noise figure (NFmin) of 1.6 dB at f=4 GHz. Remarkably, we have provided an effective route of oxide RF transistors for future high-f, high-power and low-noise RF power applications. © 2024 IEEE.

关键词：

来源：评论

学校读者我要写书评

暂无评论

1.7 kV normally-off p-GaN gate high-electron-mobility transistors on a semi-insulating SiC substrate

引用

Science China(Information Sciences) 2023年第2期66卷 250-255页

作者： Shenglei ZHAO Jincheng ZHANG Yachao ZHANG Lansheng FENG Shuang LIU Xiufeng SONG Yixin YAO Jun LUO Zhihong LIU Shengrui XU Yue HAO Key Lab of Ministry of Education for Wide Band-Gap Semiconductor Materials and Devices School of Microelectronics Xidian University School of Mechano-Electronic Engineering Xidian University Testing Center Sichuan Institute of Solid-State CircuitsChina Electronics Technology Group Corporation

A study of 1.7 kV normally-off p-GaN gate high-electron-mobility transistors(HEMTs) on SiC substrates is presented. The fabricated p-GaN HEMT with a gate-drain spacing LGD = 5 μm exhibited a threshold voltage of 1.10 V, a maximum drain current of 235 mA/mm, an ON/OFF ratio of 10～8, and a breakdown voltage of 440 V. Benefiting from the semi-insulating and high-critical-electric-field substrate, the p-GaN HEMT with LGD = 23 μm achieved the remarkably high breakdown voltage of 1740 V with substrate grounded. This breakdown voltage is very high compared with the reported values for p-GaN HEMTs on silicon substrates with substrate grounded. The vertical breakdown voltage for the p-GaN-on-SiC material exceeded 3 kV with substrate grounded. In addition, the maximum drain current at 500 K was 48% of that at 300 K with a negligible threshold voltage shift. These results indicate the substantial potential of p-GaN gate HEMTs on SiC substrates for high-voltage power applications.

关键词： p-GaN gate HEMTs high voltage SiC substrate

来源：评论

学校读者我要写书评

暂无评论

Few-shot graph learning with robust and energy-efficient memory-augmented graph neural network (MAGNN) based on homogeneous computing-in-memory

Few-shot graph learning with robust and energy-efficient mem...

引用

2022 IEEE Symposium on VLSI Technology and circuits, VLSI Technology and circuits 2022

作者： Zhang, Woyu Wang, Shaocong Li, Yi Xu, Xiaoxin Dong, Danian Jiang, Nanjia Wang, Fei Guo, Zeyu Fang, Renrui Dou, Chunmeng Ni, Kai Wang, Zhongrui Shang, Dashan Liu, Ming Key Laboratory of Microelectronics Devices and Integrated Technology Institute of Microelectronics Chinese Academy of Sciences Beijing China Department of Electrical and Electronic Engineering University of Hong Kong Hong Kong Hong Kong Rochester Institute of Technology RochesterNY United States University of Chinese Academy of Sciences Beijing China

ISBN: (纸本)9781665497725

Learning graph structured data from limited examples on-the-fly is a key challenge to smart edge devices. Here, we present the first chip-level demonstration of few-shot graph learning which homogeneously implements both the controller and associative memory of a memory-augmented graph neural network using a 1T1R resistive random-access memory (RRAM). Leveraging the in-memory computing paradigm, we validated the high end-to-end accuracy of 78% (GPU baseline 80%) and robustness on node classification of CORA dataset, while achieved 70-fold reduction in latency and 60-fold reduction in energy consumption compared with conventional digital systems. © 2022 IEEE.

关键词： Energy utilization

来源：评论

学校读者我要写书评

暂无评论

180nm BCD Technology Platform with 8V to 65V Isolated LDMOS 17

180nm BCD Technology Platform with 8V to 65V Isolated LDMOS

引用

17th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2024

作者： Ding, Qi Li, Renxiong Ning, Ning Huang, Jun Guo, Yutuo Wang, Yu He, Kunqin Liu, Yaxin Wang, Huaishan Tang, Juan Huo, Qiuyue Yuan, Minghong Peng, Pan Qiao, Ming Peng, Lulu Zhang, Bo United Microelectronics Center Co. Ltd Chongqing China University of Electronic Science and Technology of China State Key Laboratory of Electronic Thin Films and Integrated Devices Chengdu China Institute of Electronic and Information Engineering UESTC in Guangdong Dongguan China Shenzhen Institute for Advanced Study University of Electronic Science and Technology of China Shenzhen China

This work presents a 180nm BCD technology platform with 1.8V/5V CMOS, BJT, 8-65V isolated LDMOS (Lateral Double-Diffused MOSFET) and other devices such as diodes, resistors, capacitors etc., which possesses competitiv... 详细信息

ISBN: (纸本)9798350361834

关键词： MOSFET devices

来源：评论

学校读者我要写书评

暂无评论

Dynamics of ferroelectricity in monolayer AgCr2S4 calculated with a machine learning potential

引用

Physical Review B 2025年第8期111卷 085417-085417页

作者： Jinming Wu Haoran Zhu Xuanyi Li Guoliang Yu Hongyu Yu Changsong Xu Key Laboratory of Computational Physical Sciences (Ministry of Education) Institute of Computational Physical Sciences State Key Laboratory of Surface Physics and Department of Physics Fudan University Shanghai 200433 China China Key Laboratory of Fabrication Technologies for Integrated Circuits Chinese Academy of Sciences Beijing 100029 China Institute of Microelectronics Chinese Academy of Sciences Beijing 100029 China Hefei National Laboratory Hefei 230088 China

Ferroelectric materials hold significant potential for high-density nonvolatile memory applications. Understanding the dynamic mechanism of ferroelectricity is crucial for maximizing the utilization of these materials. In this study, we investigate the ferroelectric properties of monolayer AgCr2S4 by combining density functional theory (DFT) calculations with molecular dynamics (MD) simulations that utilize machine learning potentials. Our investigation reveals that the off-center displacement of Ag ions primarily drives the ferroelectricity in monolayer AgCr2S4. Remarkably, the system exhibits a high ferroelectric-paraelectric phase transition temperature of 600 K. Under low temperatures, a distinctive domain structure emerges, characterized by domain walls that induce silver vacancy defects and interstitial atoms. Moreover, ferroelectric hysteresis loops indicate that the out-of-plane and in-plane polarizations of the AgCr2S4 monolayer are switchable by applying an external electric field. Thus, our findings suggest that monolayer AgCr2S4 retains ferroelectricity at room temperature, highlighting its promising potential for applications in ferroelectric devices.

关键词： Ferroelectricity

来源：评论

学校读者我要写书评

暂无评论

Polarization-insensitive silicon intensity modulator with a maximum speed of 224 Gb/s

引用

Photonics Research 2025年第2期13卷 274-285页

作者： ZANYUN ZHANG BEIJU HUANG QIXIN WANG ZILONG CHEN KE LI KAIXIN ZHANG MEIXIN LI HAO JIANG JIAMING XING TIANJUN LIU XIAOQING LV GRAHAM T.REED Tianjin Key Laboratory of Optoelectronic Detection Technology and Systems School of Electronic and Information EngineeringTiangong UniversityTianjin 300387China Key Laboratory of Optoelectronic Materials and Devices Institute of SemiconductorsChinese Academy of SciencesBeijing 100083China Suzhou Institute of Microelectronics and Optoelectronics Integration Suzhou 215213China Key Laboratory for Biomedical Engineering of Ministry of Education Zhejiang UniversityHangzhou 310027China Peng Cheng Laboratory Shenzhen 518000China Optoelectronics Research Centre University of SouthamptonSouthampton SO171BJUK

Polarization-insensitive optical modulators allow an external laser to be remotely interconnected by single-mode optical fibers while avoiding polarization controllers,which would be convenient and cost-effective for co-packaged optics,5G,and future 6G *** this article,a polarization-insensitive silicon intensity modulator is proposed and experimentally demonstrated based on two-dimensional centrally symmetric gratings,featuring a low polarization-dependent loss of 0.15 dB in minimum and polarization insensitivity of eye *** device exhibits a low fiber-to-fiber insertion loss of 9 dB and an electro-optic(EO)bandwidth of 49.8 GHz.A modulation speed of up to 224 Gb/s is also demonstrated.

关键词： polarization controllerswhich G electro optic bandwidth polarization dependent loss G applications external laser polarization insensitive silicon intensity modulator

来源：评论

学校读者我要写书评

暂无评论

6-Inch GaN-on-Si Gold-Free Fabrication Technolgies for Monolithic Microwave Integrated circuits (MMICs)

6-Inch GaN-on-Si Gold-Free Fabrication Technolgies for Monol...

引用

IEEE Electron devices Technology and Manufacturing Conference (EDTM)

作者： Xiaojin Chen Jin Zhou Peiyu Mao Tong Wang Zhenyuan Li Hu Wei Hanghai Du Weichuan Xing Weihang Zhang Xiangdong Li Zhihong Liu Jincheng Zhang Yue Hao Key Laboratory of Wide Band Gap Semiconductor Materials and Devices School of Microelectronics Xidian University Xi'an China Guangzhou Institute of Technology Xidian University Guangzhou China

ISBN: (数字)9798331504168

ISBN: (纸本)9798331504175

We have fabricated GaN HEMTs with gate lengths of 0.5 $\mu \mathrm{m}$ and $0.25 \mu \mathrm{m}$ on 6-inch silicon-based GaN substrates using a gold-free process. The $0.5 \mu \mathrm{m}$ devices exhibit a maximum drain current density ( $\mathrm{I}_{\text{dmax}}$ ) of $680 \text{mA} / \text{mm}$ , a peak transconductance ( $\mathrm{G}_{{\max}}$ ) of $230 \text{mS} / \text{mm}$ , and small-signal characteristics with a cutoff frequency (fT) and maximum oscillation frequency (fmax) of 19 GHz and 28 GHz, respectively. Continuous wave (CW) loadpull measurements at 3.6 GHz demonstrate an output power density of $3.1 \mathrm{W} / \text{mm}$ , a peak power added efficiency (PAE) of 43.5 %, and a linear gain of 20 dB. The $0.25 \mu \mathrm{m}$ devices show a maximum drain current density (Imax) of 979 $\text{mA} / \text{mm}$ , a peak transconductance (Gmax) of $286 \text{mS} / \text{mm}$ , and small-signal characteristics with a cutoff frequency (fT) and maximum oscillation frequency (fmax) of 34 GHz and 50 GHz, respectively. CW loadpull measurements at 10 GHz yield an output power density of $2.71 \mathrm{W} / \text{mm}$ , a peak power added efficiency (PAE) of 44.5 %, and a linear gain of 12 dB. The low and uniform ohmic contact resistance (Rc) of $0.2-0.3 \Omega \cdot \text{mm}$ across the wafer indicates the potential for high-performance and cost-effective 6-inch GaN with silicon CMOS compatibility for RF applications.

关键词： Resistance Power measurement Density measurement Cutoff frequency HEMTs Silicon MODFETs Transconductance Substrates Power generation

来源：评论

学校读者我要写书评

暂无评论

Ultra-thin Body Buried In0.35Ga0.65As Channel MOSFETs with Extremely Low Off-current on Si Substrates

引用

Chinese Journal of Electronics 2021年第6期30卷 1017-1021页

作者： WANG Bo DING Peng FENG Ruize WANG Yanfu LIU Xiaoyu SUN Tangyou CHEN Yonghe LIU Xingpeng LI Qi LI Yue LIU Yingbo YIN Yihui ZHAO Hao ZHANG Wei LI Haiou JIN Zhi Guangxi Key Laboratory of Precision Navigation Technology and Application Guilin University of Electronic Technology High-Frequency High-Voltage Device and Integrated Circuits Center Institute of MicroelectronicsChinese Academy of Sciences The 34th Research Institute of China Electronics Technology Group Corporation State Key Laboratory of ASIC & System Fudan University

In this paper, we investigated the electrical properties of the Metal-oxide-semiconductor gate stack of Ti/Al2O3/In P under different annealing conditions. A minimum interface trap density of 3×1011cm-2eV-1is obtained without postmetallization annealing ***, utilizing Ti/Al2O3/In P MOS gate stack,we fabricated ultra-thin body buried In0.35 Ga0.65 As channel MOSFETs on Si substrates with optimized on/off trade-off. The 200 nm gate length device with extremely low off-current of 0.6 n A/μm, and on-off ratio of 3.3×10～5, is demonstrated by employing buried low indium(In0.35Ga0.65As) channel with In P barrier/spacer device structure, giving strong potential for future highperformance and low-power applications.

关键词： silicon gallium arsenide Si substrates size 200.0 nm minimum interface trap density III-V semiconductors As extremely low off-current postmetallization annealing treatment Si Ga In ultra-thin body optimized on-off trade-off MOSFET metal-oxide-semiconductor gate stack InP barrier-spacer device structure annealing elemental semiconductors O aluminium compounds different annealing conditions ultra-thin body buried channel MOSFET Ti-Al indium compounds interface states gate length device -InP

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：