检索结果-内蒙古大学图书馆

2024 IEEE International Electron devices Meeting, IEDM 2024

作者： Xu, Pan Jiang, Pengfei Yang, Yang Peng, Xueyang Wei, Wei Gong, Tiancheng Wang, Yuan Long, Xiao Niu, Jiebin Xu, Zhongguang Zhu, Chenxin Wu, Zhenhua Luo, Qing Liu, Ming Key Laboratory of Fabrication Technologies for Integrated Circuits Chinese Academy of Sciences Beijing China Laboratory of Microelectronics Devices and Integrated Technology Institute of Microelectronics Chinese Academy of Sciences Beijing China University of Chinese Academy of Sciences Beijing China University of Science and Technology of China Anhui Hefei China

ISBN: (纸本)9798350365429

HfO2-based FeFET paves the way for the next generation NVM thecnology, however, demands for high memory window (MW) and roubust reliability (especially the endurance) cannot be combined in the current reported devices, and the contradiction of high MW and low thermal budget (aiming for BEOL compatibility) also needs to be solved. In this work, we propose an integrated ferroelectric (FE) Hf0.5Zr0.5O2 (HZO) and amorphous In-Ga-Zn-O (a- IGZO) channel FeFET with a maximum 10V MW and prominent endurance up to 109. Workfunction (WF) engineering is utilized to regualtethe intrinsic Vt to improve the PGM/ERS efficiency with full-loop polarization switching, and the adopted Mo gate can effectively reduce the thermal budget to 300°Censuringa fully BEOL compatibility. Then with O3-plasma treatment to the gate electrode, the introduced tunneling layer can futher improve the MW by gate charge injection. The demonstrated FeFET shows great 3-bit/cell storage ability without states overlapping, high Ion/Ioff ratio (>107), as well as great linearity and high Gmax/Gmin (286) during synaptic weight modulation. © 2024 IEEE.

关键词： Budget control

来源：评论

学校读者我要写书评

暂无评论

A 256 Kbit Hf0.5Zr0.5O2-based FeRAM Chip with Scaled Film Thickness (sub-8nm), Low Thermal Budget (350oC), 100% Initial Chip Yield, Low Power Consumption (0.7 pJ/bit at 2V write voltage), and Prominent Endurance (>1012)

A 256 Kbit Hf0.5Zr0.5O2-based FeRAM Chip with Scaled Film Th...

引用

2023 International Electron devices Meeting, IEDM 2023

作者： Jiang, Pengfei Jiang, Haijun Yang, Yang Tai, Lu Wei, Wei Gong, Tiancheng Wang, Yuan Xu, Pan Lv, Shuxian Wang, Boping Gao, Jianfeng Li, Junfeng Luo, Jun Yang, Jianguo Luo, Qing Liu, Ming Shandong University School of Information Science and Engineering Qingdao China Institute of Microelectronics Chinese Academy of Sciences State Key Laboratory of Fabrication Technologies for Integrated Circuits Beijing China Institute of Microelectronics Chinese Academy of Sciences Laboratory of Microelectronics Devices and Integrated Technology Beijing China Zhangjiang Lab Shanghai China

ISBN: (纸本)9798350327670

In this work, we successfully resolve the remanent polarization (Pr) degradation issue, which is caused by the thermal budget decreasing and the film thickness scaling of Hf0.5Zr0.5O2 (HZO), and co-integrate the TiN/HZO/TiN capacitors with large initial Pr and low operating voltage in the Back-End-of -Line (BEOL) of 130nm CMOS technology to provide a 256 Kbit 1T1C FeRAM chip. Firstly, we prove that the Pr degradation is caused by the increasing component of anti-ferroelectric (AFE) phase. Then, utilizing the pre-crystallization engineering and O3 treatment to the TiN bottom electrode (BE), not only the formation of t-phase is effectively suppressed, but also the required annealing temperature is reduced. The enhancement of ferroelectricity is related to the small thermal expansion of TiO2 interface layer, which can induce large tensile stress to HZO during the annealing process. Moreover, the oxidization of TiN BE can prevent it absorbing oxygen from HZO, and the reduced oxygen vacancy (Vo) defects can improve both the retention and TDDB characteristics. Based on the above optimizations, the chip demonstrates 100% initial chip yield, >150mV sense margin after 1012 write cycles, power consumption of 0.7 pJ/bit at 2V write voltage, over 1012 endurance and 10 years retention. © 2023 IEEE.

关键词：

来源：评论

学校读者我要写书评

暂无评论

Three-dimensional Manifold Microchannel Integrated Heat Sink for High-performance Computing Chips 26

Three-dimensional Manifold Microchannel Integrated Heat Sink...

引用

26th Electronics Packaging Technology Conference, EPTC 2024

作者： Lu, Guoran Ye, Yuxin Li, Cheng Jiao, Binbin Kong, Yanmei Liu, Ruiwen Institute of Microelectronics of the Chinese Academy of Science Beijing China University of Chinese Academy of Science Beijing China Key Laboratory of Fabrication Technologies for Integrated Circuits Chinese Academy of Sciences China Beijing Microelectronics Technology Institute China

ISBN: (纸本)9798331522001

Generative AI, exemplified by ChatGPT, places heightened demands on the computational power of high-performance computing (HPC) chips, leading to an increase in power consumption. Conventional indirect cooling is limited by two layers of high thermal resistance thermal interface material (TIM), which drastically reduces thermal conduct efficiency. Direct Liquid Cooling (DLC) integrates a microfluidic cooling structure with the package lid and reduces the TIM to a single layer, providing a solution that balances performance and reliability. In this work, we proposed a three-dimensional integrated heat sink (3DIHS) along with an optimized TIM assembly process. The results show that the junction-environment thermal resistance is reduced to 0.31 K/W through process and design optimization. Also, it was implemented on a commercial FPGA device, enabling operation at maximum power levels of 56W with a temperature rise of only 20°C. This study demonstrates the effectiveness of the proposed 3DIHS in managing high heat fluxes in HPC chips. © 2024 IEEE.

关键词：

来源：评论

学校读者我要写书评

暂无评论

Threshold-independent method for single-shot readout of spin qubits in semiconductor quantum dots

引用

Chinese Physics B 2024年第1期33卷 274-279页

作者：胡睿梓祝圣凯张鑫周圆倪铭马荣龙罗刚孔真真王桂磊曹刚李海欧郭国平 CAS Key Laboratory of Quantum Information University of Science and Technology of ChinaHefei 230026China CAS Center For Excellence in Quantum Information and Quantum Physics University of Science and Technology of ChinaHefei 230026China Key Laboratory of Microelectronics Devices and Integrated Technology Institute of MicroelectronicsChinese Academy of SciencesBeijing 100029China Beijing Superstring Academy of Memory Technology Beijing 100176China Origin Quantum Computing Company Limited Hefei 230026China

The single-shot readout data process is essential for the realization of high-fidelity qubits and fault-tolerant quantum algorithms in semiconductor quantum dots. However, the fidelity and visibility of the readout process are sensitive to the choice of the thresholds and limited by the experimental hardware. By demonstrating the linear dependence between the measured spin state probabilities and readout visibilities along with dark counts, we describe an alternative threshold-independent method for the single-shot readout of spin qubits in semiconductor quantum dots. We can obtain the extrapolated spin state probabilities of the prepared probabilities of the excited spin state through the threshold-independent method. We then analyze the corresponding errors of the method, finding that errors of the extrapolated probabilities cannot be neglected with no constraints on the readout time and threshold voltage. Therefore, by limiting the readout time and threshold voltage, we ensure the accuracy of the extrapolated probability. We then prove that the efficiency and robustness of this method are 60 times larger than those of the most commonly used method. Moreover, we discuss the influence of the electron temperature on the effective area with a fixed external magnetic field and provide a preliminary demonstration for a single-shot readout of up to 0.7K/1.5T in the future.

关键词： quantum computation quantum dot quantum state readout

来源：评论

学校读者我要写书评

暂无评论

1.27 GW/cm² Reverse Blocking E-Mode GaN-Si(100) Monolithic Heterogeneous Integration Cascode Switch With Ultralow Turn-On Voltage and Dynamic RON

IEEE Electron Device Letters

引用

IEEE Electron Device Letters 2025年第5期46卷 805-808页

作者： Fan, Yutong Zhang, Weihang Zhang, Yachao Wu, Yinhe Feng, Xin Liu, Zhihong Jiang, Yang In Mak, Pui Hao, Yue Zhang, Jincheng Xidian University National Key Laboratory of Wide Bandgap Semiconductor Devices and Integrated Technology School of Microelectronics Xi'an710071 China Guangzhou Institute of Technology Xidian University Guangzhou Wide Bandgap Semiconductor Innovation Center Guangzhou510555 China Institute of Microelectronics University of Macau State Key Laboratory of Analog and Mixed-Signal Vlsi China

In this letter, an E-Mode GaN-Si(100) monolithic heterogeneous integration cascode switch (RBMHIC-switch) with reverse blocking compatibility on a SiC substrate with an AlN buffer layer is demonstrated. The RBMHIC-switch with LGD of 22~μ m showed a threshold voltage (VTH) of 2.64 V, a large forward gate voltage swing of 16.27 V, a turn-on voltage (VON) of 0.3 V, and an extremely low reverse leakage current (IR) of 3.5× 10-4 mA/mm at -2000 V. The forward breakdown voltage (VFBR) of 2264 V and reverse breakdown voltage (VRBR) of 2183 V with a specific on-resistance (RON, SP ) of 3.74 mΩ ċ cm2 were achieved, resulting in a forward power figure of merit (PFOM = V BR2 /RON,SP) of 1.35 GW/cm2 and reverse PFOM of 1.27 GW/cm2. The ratio between dynamic-RON and static-RON was 1.104 and 1.127 after a 10 ms 1900 V drain stress voltage (V DS- OFF ) and a 10 ms -1900 V V DS- OFF (delay time = 1~μ s) for the RBMHIC-switches, respectively, which were the best among all existing GaN power devices with reverse blocking capability. The thermal resistance at different temperatures was also extracted. The RBMHIC-switche shows decent overall characteristics as compared to the reported results. © 1980-2012 IEEE.

关键词： Gallium nitride

来源：评论

学校读者我要写书评

暂无评论

Investigation of performance-enhanced GaN-based E-mode pchannel MOSFET with pre-ohmic-annealing treatment

引用

Journal of Semiconductors 2024年第11期45卷 63-68页

作者： Huake Su Tao Zhang Shengrui Xu Hongchang Tao Yibo Wang Yuan Gao Yue Hao Jincheng Zhang State Key Laboratory of Wide-bandgap Semiconductor Devices and Integrated Technology School of MicroelectronicsXidian UniversityXi’an 710071China Suzhou Institute of Nano-Tech and Nano-Bionics(SINANO) Chinese Academy of SciencesSuzhou 215123China

Pre-ohmic-annealing(POA)treatment of P-GaN/AlN/AlGaN epitaxy under N_(2)atmosphere was demonstrated to effectively achieve good p-type ohmic contact as well as decreased epitaxy sheet *** contact resistance(Rc)extracted by transfer length method reduced from 38 to 23Ω·mm with alleviated contact barrier height from 0.55 to 0.51 eV after POA treatment.X-ray photoelectron spectroscopy and Hall measurement confirmed that POA treatment was able to reduce surface state density and improve the hole concentration of *** to the decreased Rc and improved two-dimensional hole gas(2DHG)density,an outstanding-performance GaN E-mode p-channel MOSFET was successfully realized.

关键词： POA treatment GaN p-channel E-Mode barrier height surface states

来源：评论

学校读者我要写书评

暂无评论

Analytical workload dependence of self-heating effect for SOI MOSFETs considering two-stage heating process

引用

Chinese Physics B 2023年第9期32卷 522-529页

作者：李逸帆倪涛李晓静王娟娟高林春卜建辉李多力蔡小五许立达李雪勤王润坚曾传滨李博赵发展罗家俊韩郑生 Institute of Microelectronics Chinese Academy of SciencesBeijing 100029China University of Chinese Academy of Sciences Beijing 100049China Key Laboratory of Science and Technology on Silicon Devices Chinese Academy of SciencesBeijing 100029China

Dynamic self-heating effect(SHE)of silicon-on-insulator(SOI)MOSFET is comprehensively evaluated by ultrafast pulsed I-V measurement in this *** is found for the first time that the SHE complete heating response and cooling response of SOI MOSFETs are conjugated,with two-stage curves *** establish the effective thermal transient response model with stage superposition corresponding to the heating *** systematic study of SHE dependence on workload shows that frequency and duty cycle have more significant effect on SHE in first-stage heating process than in the second *** the first-stage heating process,the peak lattice temperature and current oscillation amplitude decrease by more than 25 K and 4%with frequency increasing to 10 MHz,and when duty cycle is reduced to 25%,the peak lattice temperature drops to 306 K and current oscillation amplitude decreases to 0.77%.Finally,the investigation of two-stage(heating and cooling)process provides a guideline for the unified optimization of dynamic SHE in terms of *** the operating frequency is raised to GHz,the peak temperature depends on duty cycle,and self-heating oscillation is completely suppressed.

关键词： self-heating effect(SHE) silicon-on-insulator(SOI)MOSFETs thermal transient response workload

来源：评论

学校读者我要写书评

暂无评论

Multiple SiGe/Si layers epitaxy and SiGe selective etching for vertically stacked DRAM

引用

Journal of Semiconductors 2023年第12期44卷 133-140页

作者： Zhenzhen Kong Hongxiao Lin Hailing Wang Yanpeng Song Junjie Li Xiaomeng Liu Anyan Du Yuanhao Miao Yiwen Zhang Yuhui Ren Chen Li Jiahan Yu Jinbiao Liu Jingxiong Liu Qinzhu Zhang Jianfeng Gao Huihui Li Xiangsheng Wang Junfeng Li Henry HRadamson Chao Zhao Tianchun Ye Guilei Wang Key Laboratory of Microelectronics Devices&Integrated Technology Institute of MicroelectronicsChinese Academy of SciencesBeijing 100029China Beijing Superstring Academy of Memory Technology Beijing 100176China Research and Development Center of Optoelectronic Hybrid IC Guangdong Greater Bay Area Institute of Integrated Circuit and SystemGuangzhou 510535China Microelectronics Institute University of Chinese Academy of SciencesBeijing 100049China Hefei National Laboratory Hefei 230088China

Fifteen periods of Si/Si_(0.7)Ge_(0.3)multilayers(MLs)with various Si Ge thicknesses are grown on a 200 mm Si substrate using reduced pressure chemical vapor deposition(RPCVD).Several methods were utilized to characterize and analyze the ML *** high resolution transmission electron microscopy(HRTEM)results show that the ML structure with 20 nm Si_(0.7)Ge_(0.3)features the best crystal quality and no defects are *** Si_(0.7)Ge_(0.3)ML structures etched by three different methods were carried out and compared,and the results show that they have different selectivities and *** this work,the fabrication process influences on Si/Si Ge MLs are studied and there are no significant effects on the Si layers,which are the channels in lateral gate all around field effect transistor(L-GAAFET)*** vertically-stacked dynamic random access memory(VS-DRAM),it is necessary to consider the dislocation caused by strain accumulation and stress release after the number of stacked layers exceeds the critical *** results pave the way for the manufacture of high-performance multivertical-stacked Si nanowires,nanosheet L-GAAFETs,and DRAM devices.

关键词： RPCVD epitaxy SiGe/Si multilayers L-GAAFETs VS-DRAM

来源：评论

学校读者我要写书评

暂无评论

First Demonstration of a Design Methodology for Highly Reliable Operation at High Temperature on 128kb 1T1C FeRAM Chip

First Demonstration of a Design Methodology for Highly Relia...

引用

2023 IEEE Symposium on VLSI Technology and circuits, VLSI Technology and circuits 2023

作者： Gong, Tiancheng Xu, Lihua Wei, Wei Jiang, Pengfei Yuan, Peng Nie, Bowen Huang, Yuanquan Wang, Yuan Yang, Yang Gao, Jianfeng Li, Junfeng Luo, Jun Wang, Lingfei Yang, Jianguo Luo, Qing Li, Ling Chung, Steve S. Liu, Ming Institute of Microelectronics Chinese Academy of Sciences State Key Laboratory of Fabrication Technologies for Integrated Circuits Beijing China Institute of Microelectronics Chinese Academy of Sciences Laboratory of Microelectronics Devices and Integrated Technology Beijing China Institute of Electronics National Yang Ming Chiao Tung University Taiwan

ISBN: (纸本)9784863488069

In achieving a reliable operation of FRAM arrays at high temperature (300K-400K), we provide an optimized operation design methodology considering the temperature effect on 128kb ITIC FRAM chip for the first time. Firstly, we found that the conventional voltage selection scheme in ITIC FRAM array is not applicable at high temperature since the Pr value read by low voltage decreases at high temperature, leading to a poor yield. Then, the mechanism of Pr degradation under high temperature is systematically investigated through material characterizations and electrical measurements. It was found that the increase of the internal electric field (Ebias) caused by electron de-trapping mainly contributes to the Pr degradation. Moreover, a KMC model considering Ebias is developed, and the optimum voltage, which can mitigate the temperature effect from 300K-400K, is predicted. This predicted voltage is finally validated on 128kb ITIC FeRAM chip, and excellent properties including non-volatile (150°C >106s) and high endurance (>1011) under the predicted voltage are also demonstrated. © 2023 JSAP.

关键词： Temperature

来源：评论

学校读者我要写书评

暂无评论

Ultra-high-Q photonic crystal nanobeam cavity for etchless lithium niobate on insulator(LNOI)platform

引用

Opto-Electronic Advances 2025年第1期8卷 59-70页

作者： Zhi Jiang Cizhe Fang Xu Ran Yu Gao Ruiqing Wang Jianguo Wang Danyang Yao Xuetao Gan Yan Liu Yue Hao Genquan Han State Key Laboratory of Wide-Bandgap Semiconductor Devices and Integrated Technology School of MicroelectronicsXidian UniversityXi’an 710071China Key Laboratory of Light Field Manipulation and Information Acquisition Ministry of Industry and Information Technologyand Shaanxi Key Laboratory of Optical Information TechnologySchool of Physical Science and TechnologyNorthwestern Polytechnical UniversityXi’an 710129China Hangzhou Institute of Technology Xidian UniversityHangzhou 311200China

The expansive spectral coverage and superior optical properties of lithium niobate(LN)offer a comprehensive suite of tools for exploring novel *** high-quality(Q)photonic resonator cavities is crucial for enhancing light-matter ***,this task is challenging as the device performance is heavily dependent on the fabrication quality of the *** this paper,we present experimental validation of an etchless approach to fabricating high-Q photonic crystal nanobeam cavities(PCNBCs).We successfully fabricate PCNBCs with Q factors exceeding 105 while maintaining high transmittance by capitalizing on the low waveguide loss and high fabrication tolerance of TE-polarized ***,the Q factor achieved here exceeds previous reports on etchless LN PCNBCs by over an order of *** from this advancement,we further explore a variety of optical functions,including thermo-optic tuning,optically induced bistability,and Fano line shapes *** findings present promising prospects for a versatile platform technique,facilitating the development of high-performance electro-optic or acousto-optic modulators,optical logic devices,and quantum photonics,highlighting its significant impact in the field of photonic integration.

关键词： photonic crystal nanobeam cavity LNOI platform high Q thermo-optic tuning bistability Fano line shapes

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：