检索结果-内蒙古大学图书馆

Electronics Design Automation (ISEDA), International Symposium of

作者： Zhangyu Li Tun Li Chang Liu Liang Wang Chunxue Liu Yang Guo Wanxia Qu Colledge of Computer Science and Technology National University of Defense Technology Changsha P. R. China Key Laboratory of Advanced Microprocessor Chips and Systems Changsha P. R. China Beijing Microelectronics Technology Institute Beijing P. R. China

ISBN: (数字)9798350352030

ISBN: (纸本)9798350352047

With the rapid development of integrated circuit manufacturing processes, soft errors have emerged as a pivotal factor that influences circuit reliability. This paper endeavors to investigate the rapid estimation of the impact of the single event upset (SEU) on the logic behaviors of flip-flops in a circuit using machine learning methods. A major challenge currently faced when applying machine learning methods for SEU evaluation is the absence of publicly available circuit datasets. Therefore, this paper employs the fault injection method to acquire circuit data such as soft error sensitivity. Subsequently, it models the gate-level netlist and integrates the netlist models with the acquired data to construct a dataset. Finally, a model based on graph at-tention network (GAT) is developed and we use the leave-one-out cross validation method to evaluate the performance. Compared to neural network methods skilled at handling structured data, the experimental results indicate that the method proposed in this paper has better predictive performance. It achieves an average absolute error of 0.064, representing a 43.46 % improvement over the baseline.

关键词： Sensitivity Manufacturing processes Neural networks Single event upsets Machine learning Logic gates Data models

来源：评论

学校读者我要写书评

暂无评论

Corrigendum to “A soft-error-tolerant, 1.25 GHz to 3.125 GHz, 3.18 ps RMS-jitter CPPLL in 40 nm CMOS process” [Microelectron. Reliab. volume 124 (2021) 114337]

引用

microelectronics Reliability 2022年 135卷

作者： Qiancheng Guo Yang Guo Bin Liang JianJun Chen Xi Chen Institute of Microelectronics and Microprocessor School of Computer National University of Defense Technology Changsha HN China

来源：评论

学校读者我要写书评

暂无评论

Dual-issue CGRA for DAG acceleration 4th

Dual-issue CGRA for DAG acceleration

引用

4th International Conference of Pioneer Computer Scientists, Engineers and Educators, ICPCSEE 2018

作者： Zhou, Li Zhang, Jianfeng Liu, Hengzhu Institute of Microprocessor and Microelectronics School of Computer National University of Defense Technology ChangshaHunan410073 China

ISBN: (纸本)9789811322020

Coarse-grained Reconfigurable Array (CGRA) is suitable candidate hardware architecture for many computation-intensive applications due to its flexibility and efficiency. In current CGRA architecture, each Processing Element (PE) in CGRA performs one operation or transfers data onto neighbors per cycle. In this paper, a dual-issue scheme is proposed to execute Data Acyclic Graph (DAG). Two operations with mutual precedents can be executed at the same cycle in the PE in the proposed design to improve efficiency. Since some hardware is shared by operations, the overhead can be lowered. We also proposed an ant colony based algorithm for mapping DAG to dual-issue CGRA. Experimental results demonstrate that dual-issue CGRA consumes 5.24% less hardware resource while the performance of some DAG improved 2.6%. © Springer Nature Singapore Pte Ltd. 2018.

关键词： Mapping

来源：评论

学校读者我要写书评

暂无评论

Dual-Issue CGRA for DAG Acceleration

Dual-Issue CGRA for DAG Acceleration

引用

2018国际计算机前沿大会（原国际青年计算机大会）

作者： Li Zhou Jianfeng Zhang Hengzhu Liu Institute of Microprocessor and Microelectronics School of ComputerNational University of Defense Technology

Coarse-grained Reconfigurable Array(CGRA) is suitable candidate hardware architecture for many computation-intensive applications due to its flexibility and efficiency. In current CGRA architecture, each Processing Element(PE) in CGRA performs one operation or transfers data onto neighbors per *** this paper, a dual-issue scheme is proposed to execute Data Acyclic Graph(DAG). Two operations with mutual precedents can be executed at the same cycle in the PE in the proposed design to improve efficiency. Since some hardware is shared by operations, the overhead can be lowered. We also proposed an ant colony based algorithm for mapping DAG to dual-issue CGRA. Experimental results demonstrate that dual-issue CGRA consumes 5.24% less hardware resource while the performance of some DAG improved 2.6%.

关键词： CGRA Dual-issue DAG mapping

来源：评论

学校读者我要写书评

暂无评论

An efficient parallel SURF algorithm for multi-core processor

An efficient parallel SURF algorithm for multi-core processo...

引用

16th National Conference on Computer Engineering and Technology, NCCET 2012

作者： Liu, Zhong Xing, Binchao Chen, Yueyue Microelectronics and Microprocessor Institute School of Computer National University of Defense Technology Changsha China

ISBN: (纸本)9783642358975

In this paper, we propose an efficient parallel SURF algorithm for multi-core processor, which adopts data-level parallel method to implement parallel keypoints extraction and matching. The computing tasks are assigned to four DSP cores for parallel processing. The multi-core processor utilizes QLink and SDP respectively to deal with data communication and synchronization among DSP cores, which fully develops the multi-level parallelism and the strong computing power of multi-core processor. The parallel SURF algorithm is fully tested based on 5 different image samples with scale change, rotation, change in illumination, addition of noise and affine transformation The experimental results show that the parallel SURF algorithm has good adaptability for various distorted images, good image matching ability close to the sequential algorithm and the average speedup is 3.61. © 2013 Springer-Verlag.

关键词： Image matching

来源：评论

学校读者我要写书评

暂无评论

Mapping loops onto coarse-grained reconfigurable array using genetic algorithm

Mapping loops onto coarse-grained reconfigurable array using...

引用

8th International Conference on Bio-Inspired Computing: Theories and Applications, BIC-TA 2013

作者： Zhou, Li Liu, Dongpei Tang, Min Liu, Hengzhu Institute of Microelectronics and Microprocessor School of Computer Science National University of Defense Technology Changsha China

ISBN: (纸本)9783642375019

Coarse-grained reconfigurable array (CGRA) is a competitive hardware platform for computation intensive tasks in many application domains. The performance of CGRA heavily depends on the mapping algorithm which exploits different level of parallelisms. Unfortunately, the mapping problem on CGRA is proved to be NP-complete. In this paper, we propose a genetic based modulo scheduling algorithm to map application kernels onto CGRA. An efficient routing heuristic is also presented to reduce the mapping time. Experiment result shows our algorithm outperforms other heuristic algorithms both in solution’s quality and mapping time. © Springer-Verlag Berlin Heidelberg 2013.

关键词： Genetic algorithms

来源：评论

学校读者我要写书评

暂无评论

Mapping loops onto Coarse-grained reconfigurable array using genetic algorithm

Advances in Intelligent Systems and Computing

引用

Advances in Intelligent Systems and Computing 2013年 212卷 801-808页

作者： Zhou, Li Liu, Dongpei Tang, Min Liu, Hengzhu Institute of Microelectronics and Microprocessor School of Computer Science National University of Defense Technology Changsha China

ISBN: (纸本)9783642375019

Coarse-grained reconfigurable array (CGRA) is a competitive hardware platform for computation intensive tasks in many application domains. The performance of CGRA heavily depends on the mapping algorithm which exploits different level of parallelisms. Unfortunately, the mapping problem on CGRA is proved to be NP-complete. In this paper, we propose a genetic based modulo scheduling algorithm to map application kernels onto CGRA. An efficient routing heuristic is also presented to reduce the mapping time. Experiment result shows our algorithm outperforms other heuristic algorithms both in solution's quality and mapping time. © Springer-Verlag Berlin Heidelberg 2013.

关键词： Genetic algorithms

来源：评论

学校读者我要写书评

暂无评论

A Cluster-based Coarse Grained Reconfigurable Array Architecture

A Cluster-based Coarse Grained Reconfigurable Array Architec...

引用

第十七届计算机工程与工艺年会暨第三届微处理器技术论坛

作者： Zhou Li Liu Hengzhu Liu Dongpei Institute of Microprocessor and Microelectronics School of ComputerNational University of Defense Technology

Coarse grained reconfigurable array(CGRA) is an architecture which offers hardware like high performance and software like *** two characteristics make CGRA an effective candidate for computational intensive *** this paper,a novel cluster-base CGRA architecture is *** composed of a number of reconfigurable clusters which consist of generic processing elements and shared processing *** to the resource sharing and local connectivity,cluster-based CGRA achieves better resource utilization and higher efficiency compared to conventional *** is reduced and the performance can be *** showed that the proposed cluster-base CGRA outperforms some existing architectures.

关键词： CGRA cluster-based architecture resource sharing

来源：评论

学校读者我要写书评

暂无评论

Mapping DAG to CGRA Using Min-Max Ant Colony System

Mapping DAG to CGRA Using Min-Max Ant Colony System

引用

International Conference on Cyber-Enabled Distributed Computing and Knowledge Discovery, CyberC

作者： Li Zhou Hengzhu Liu Institute of Microelectronics and Microprocessor National University of Defense Technology Changsha China

ISBN: (纸本)9781479913275

Coarse-grained reconfigurable array (CGRA) architecture has become popular because of its performance and flexibility. The efficiency of CGRA relies on an efficient application mapping algorithm to exploit parallelisms. In this paper, we formalized the temporal mapping problem and proposed the min-max ant colony system (MMAS) algorithm for CGRA mapping. Further optimization of MMAS is studied to reduce mapping time while maintaining the quality of solutions. Comparisons with other heuristic algorithms show that our approach obtains better results in less mapping time.

关键词： Signal processing algorithms Kernel Optimization Cities and towns Algorithm design and analysis Heuristic algorithms Computer architecture

来源：评论

学校读者我要写书评

暂无评论

Parallelized cyclostationary feature detection on a software defined radio processor

Parallelized cyclostationary feature detection on a software...

引用

International Symposium on Signals, Systems and Electronics

作者： Wang, Shixian Zhang, Botao Liu, Hengzhu Xie, Lunguo Institute of Microelectronics and Microprocessor School of Computer National University of Defense Technology Changsha HN China

ISBN: (纸本)9781424463558

The accurate and timely spectrum sensing ability is very critical to cognitive radio. Cyclostationary feature detection has the ability to separate the signal of interest from noise and/or interference, but the computational complexity of cyclic spectral analysis limits its use as a signal analysis tool. To reduce the computational complexity of cyclic spectral analysis, this paper proposes an efficient parallel FFT accumulation method (FAM) algorithm and realizes it on a novel SDR processor for next generation wireless communication, GAEA. The simulation results show the parallel FAM algorithm's processing time on an 8 MHz BW signal at frequency resolution of 512 Hz requires approximately 78.8 ms. This approach will be suitable for spectrum sensing of cognitive radio and other cyclostationary feature detection applications. © 2010 IEEE.

关键词： Cognitive radio

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：