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China Semiconductor Technology International Conference (CSTIC)

作者： Shuhan Liu Tianyi Liu Zhiyuan Fu Cheng Chen Qianqian Huang Ru Huang Key Laboratory of Microelectronic Devices and Circuits (MOE) Institute of Microelectronics Peking University Beijing China

ISBN: (数字)9781728165585

ISBN: (纸本)9781728165592

In this work, a novel bio-inspired hardware design of lateral divisive inhibition is proposed and demonstrated by using only one transistor of ferroelectric FET. The proposed design is simulated based on our developed FeFET model, and is also proved to be functional in spiking neural network. The new design with ultra-low hardware cost exhibits good biological plausibility, showing its great potential for neuromorphic computing.

关键词： Neuromorphic engineering Computational modeling Biological system modeling Neural networks Hardware Transistors Task analysis

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Resistive Memory-based Neural Differential Equation Solver for Score-based Diffusion Model

arXiv

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arXiv 2024年

作者： Yang, Jichang Chen, Hegan Chen, Jia Wang, Songqi Wang, Shaocong Yu, Yifei Chen, Xi Wang, Bo Zhang, Xinyuan Cui, Binbin Li, Yi Lin, Ning Xu, Meng Li, Yi Xu, Xiaoxin Qi, Xiaojuan Wang, Zhongrui Zhang, Xumeng Shang, Dashan Wang, Han Liu, Qi Cheng, Kwang-Ting Liu, Ming Department of Electrical and Electronic Engineering the University of Hong Kong Hong Kong ACCESS – AI Chip Center for Emerging Smart Systems InnoHK Centers Hong Kong Science Park Hong Kong Laboratory of Microelectronic Devices and Integrated Technology Institute of Microelectronics Chinese Academy of Sciences Beijing100029 China State Key Laboratory of Integrated Chips and Systems Frontier Institute of Chip and System Fudan University Shanghai200433 China Institute of the Mind the University of Hong Kong Hong Kong University of Chinese Academy of Sciences Beijing100049 China School of Integrated Circuits Hubei Key Laboratory for Advanced Memories Huazhong University of Science and Technology Wuhan430074 China Department of Electronic and Computer Engineering the Hong Kong University of Science and Technology Hong Kong

Human brains image complicated scenes when reading a novel. Replicating this imagination is one of the ultimate goals of AI-Generated Content (AIGC). However, current AIGC methods, such as score-based diffusion, are still deficient in terms of rapidity and efficiency. This deficiency is rooted in the difference between the brain and digital computers. Digital computers have physically separated storage and processing units, resulting in frequent data transfers during iterative calculations, incurring large time and energy overheads. This issue is further intensified by the conversion of inherently continuous and analog generation dynamics, which can be formulated by neural differential equations, into discrete and digital operations. Inspired by the brain, we propose a time-continuous and analog in-memory neural differential equation solver for score-based diffusion, employing emerging resistive memory. The integration of storage and computation within resistive memory synapses surmount the von Neumann bottleneck, benefiting the generative speed and energy efficiency. The closed-loop feedback integrator is time-continuous, analog, and compact, physically implementing an infinite-depth neural network. Moreover, the software-hardware co-design is intrinsically robust to analog noise. We experimentally validate our solution with 180 nm resistive memory in-memory computing macros. Demonstrating equivalent generative quality to the software baseline, our system achieved remarkable enhancements in generative speed for both unconditional and conditional generation tasks, by factors of 64.8 and 156.5, respectively. Moreover, it accomplished reductions in energy consumption by factors of 5.2 and 4.1. Our approach heralds a new horizon for hardware solutions in edge computing for generative AI applications. © 2024, CC BY-NC-SA.

关键词： Diffusion

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Deep-Learning-Enhanced Single-Spin Readout in Silicon Carbide at Room Temperature

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Physical Review Applied 2022年第3期17卷 034046-034046页

作者： Yu-Wei Liao Qiang Li Mu Yang Zheng-Hao Liu Fei-Fei Yan Jun-Feng Wang Ji-Yang Zhou Wu-Xi Lin Yi-Dan Tang Jin-Shi Xu Chuan-Feng Li Guang-Can Guo CAS Key Laboratory of Quantum Information University of Science and Technology of China Hefei 230026 People’s Republic of China CAS Center For Excellence in Quantum Information and Quantum Physics University of Science and Technology of China Hefei 230026 People’s Republic of China High-Frequency High-Voltage Devices and Integrated Circuits R&D Center Institute of Microelectronics of Chinese Academy of Sciences 100029 Beijing China

Defect spin qubits in silicon carbide have recently drawn widespread attention. Extraction of spin information in the presence of noise always requires multiple repeated measurements, which consumes a large amount of time resources. In this paper, we propose a deep-learning-enhanced method to extract effective parameters from continuous-wave optically detected magnetic resonance (ODMR) spectra and Rabi oscillations with less time consumption. Even if the signal-to-noise ratio is reasonably low, a well-trained convolutional neural network (CNN) can predict the resonance peaks of ODMR spectra or the period of Rabi oscillations. Because of the fast output of predictions by the CNN, this method can be used to sense the magnetic field in the environment and microwave intensities in real time.

关键词： Coherent control Color centers Crystal defects Quantum information with solid state qubits Semiconductor compounds Artificial neural networks Machine learning Optically detected magnetic resonance

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Multi-Classification of Cardiovascular Diseases Based on Heart Sound Signals Using Audio Spectrogram Features with Pure Attention Transformer

SSRN

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SSRN 2022年

作者： Yang, Dongru Lin, Yi Wei, Jianwen Lin, Xiongwei Zhao, Xiaobo Yao, Yingbang Tao, Tao Liang, Bo Lu, Sheng-Guo Guangdong Provincial Research Center on Smart Materials and Energy Conversion Devices Guangdong Provincial Key Laboratory of Functional Soft Condensed Matter School of Integrated Circuits School of Materials and Energy Guangdong University of Technology Guangzhou510006 China School of Microelectronics Shenzhen Institute of Information Technology Shenzhen518000 China

Background and objectives: In computer-aided medical diagnosis or prognosis, the automatic classification of cardiovascular diseases (CVDs) based on heart sound (HS) signals is of great importance since the heart sound signal contains a wealth of information that can reflect the cardiovascular status. Traditional binary classification algorithms (normal and abnormal) currently cannot comprehensively assess CVDs based on analyzing various heart sounds. The differences between heart sound signals are relatively subtle, but the reflected heart conditions differ significantly. Consequently, the multiclassification of CVDs from heart sound signals is of utmost importance from a clinical ***: For the multi-classification of heart sound signals, we propose a creative non-convolutional neural networks (CNN) pure-attention transformer model. It has achieved remarkable results from four abnormal HS signals and the typical ***: According to a fivefold cross-validation strategy, the proposed method achieves a mean classification accuracy of 99% and a mean average precision of 0.99. Further, the classification accuracy for Aortic Stenosis (AS), Mitral Regurgitation (MR), Mitral Stenosis (MS), Mitral Valve Prolapse (MVP), and standard heart sound signals (N) is 99.39%, 99.53%, 99.42%, 99.48%, and 99.67%, ***: The results indicate that the framework can precisely classify five classes of heart sound signals. Our method provides an efficient tool for CVD multi-classification based on heart sound signals in clinical settings. © 2022, The Authors. All rights reserved.

关键词： Heart

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Geometric Variability Aware Quantum Potential based Quasi-ballistic Compact Model for Stacked 6 nm-Thick Silicon Nanosheet GAA-FETs

Geometric Variability Aware Quantum Potential based Quasi-ba...

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International Electron devices Meeting (IEDM)

作者： Shijie Huang Zhenghua Wu Haoqing Xu Jingrui Guo Lihua Xu XinLv Duan Qian Chen Guanhua Yang Qingzhu Zhang Huaxiang Yin Lingfei Wang Ling Li Ming Liu Key Laboratory of Microelectronics Devices and Integrated Technology Institute of Microelectronics of the Chinese Academy of Sciences Beijing China University of Chinese Academy of Sciences Beijing China Advanced Integrated Circuits R&D Center Institute of Microelectronic of the Chinese Academy of Sciences Beijing China

Quantum-corrected quasi-ballistic compact model is developed for Stacked Silicon Nanosheet (SiNS) Gate-all-around (GAA) FETs. Theories of Density-Gradient-Poisson (DG-P), Singular perturbation and quasi-ballistic to interpret quantum mechanicals on density profile and charge transport are employed in analytical expressions of current, terminal charge and trans-capacitance. Besides, the model incorporates ultra-scaling induced subthreshold degradation and is rigidly verified by comparing to 6-nm-thick-SiNS based experiments (of both ${P-}$ and $N$ -GAAFET) and GTS simulations (of down to 15 nm channel length). Instead of classical Schrodinger-Poisson theory, it holds features of computation-efficiency and SPICE-compatibility. Especially, awareness of geometric variability enables performance and reliability assessments that statistical effects of stacked nanosheets on on-state voltage are predicted. Hence, this high-efficient quantum corrected model is promising in designing integrated circuits and developing a geometry aware design-technology co-optimization flow in the next generation technology node.

关键词： Electric potential Simulation Field effect transistors Gallium arsenide Logic gates Mathematical models Silicon

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Low power and high uniformity of HfOx-based RRAM via tip-enhanced electric fields

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中国科学:化学（英文版） 2019年第10期62卷 160-166页

作者： Xiaokang LI Baotong ZHANG Bowen WANG Xiaoyan XU Yuancheng YANG Shuang SUN Qifeng CAI Shijie HU Xia AN Ming LI Ru HUANG Key Laboratory of Microelectronic Devices and Circuits(MOE) Institute of MicroelectronicsPeking University Beijing 100871 China

In this paper,the HfOx-based resistive random access memory (RRAM) devices with sub-100 nm pyramid-type electrodes were *** the help of tip-enhanced electric field around the pyramid-type electrodes,it was experimentally demonstrated that the novel devices have better cycle-to-cycle variation control,lower forming/set voltage (1.97/0.7 V) and faster switching speed (≤ 30 ns under 0.9 V pulse) as well as better endurance reliability than conventional flat electrode resistive memory *** addition,the novel RRAM is experimentally demonstrated with independence of electrode number for the first time to present great potential in scaling *** novel structure metal-oxide based RRAM will be suitable for the future low-power non-volatile memory application.

关键词： RRAM pyramid-type electrode variation reliability switching speed conducting filament

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A 1μW-to-158μW Output Power Pseudo Open-Loop Boost DC-DC with 86.7% Peak Efficiency using Frequency-Programmable Oscillator and Hybrid Zero Current Detection

A 1μW-to-158μW Output Power Pseudo Open-Loop Boost DC-DC w...

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IEEE International Symposium on circuits and Systems (ISCAS)

作者： Xiaolong Chen Enbin Gong Hao Zhang Le Ye Ru Huang Key Laboratory of Microelectronic Devices and Circuits (MOE) Institute of Microelectronics Peking university Beijing 100871 China

ISBN: (数字)9781728133201

ISBN: (纸本)9781728133218

This paper proposed a pseudo-open boost DC-DC converter whose input voltage ranges from 300mV-to-500mV and output voltage ranges from 1.2V-to-1.8V. The output power ranges from 1μW to 158μW. Three key structures are designed to realize the high energy conversion efficiency when the load reaches ultra-light: the pseudo open-loop structure, the frequency-programmable oscillator, and the hybrid zero current detection (H-ZCD) circuit. The pseudo open-loop structure eliminates the analog comparators or error amplifiers used in converter and the quiescent power loss is much reduced. The frequency-programmable ring oscillator is able to output 9-bit binary frequency ranges from 500Hz-100KHz, so the power consumption of clock generation is saved when load power reaches to ultra-light. The proposed H-ZCD is designed to reduce the inductor power loss with just tiny power consumption. Accordingly, the high efficiency boost DC-DC works in the discontinuous condition mode (DCM) and the constant on time pulse frequency modulation (PFM) is proposed. As a simulation result, the peak efficiency of the converter reaches to 86.7% while the load power is 13.7μW.

关键词： Ring oscillators DC-DC power converters Power demand Switches Capacitors Energy efficiency

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An 81–99 GHz Tripler with Fundamental Cancellation and 3rd Harmonic Enhancement Technique in 40-nm CMOS

An 81–99 GHz Tripler with Fundamental Cancellation and 3rd ...

引用

IEEE International Symposium on circuits and Systems (ISCAS)

作者： Xiaolei Su Xiucheng Hao Dong Wang Zhengkun Shen Zexue Liu Junhua Liu Huailin Liao Key Laboratory of Microelectronic Devices and Circuits (MOE) Institute of Microelectronics Peking University Beijing 100871 China

ISBN: (数字)9781728133201

ISBN: (纸本)9781728133218

An 81–99 GHz tripler for wireless transceiver LO generation is presented in this paper. To suppress the fundamental signal and enhance the 3rd harmonic, the inversion signal is applied to the gate of the cascading transistor of the push-push differential pair. A capacitor is connected to the source and drain of the cascading transistor to further suppress the fundamental signal. Without additional filters, the tripler achieves more than 40 dBc of fundamental suppression with an even harmonic suppression of up to 60 dBc. The tripler reaches an output power of −2.6 dBm (4-dBm input) at 91.5 GHz with a 20% bandwidth of from 81 to 99 GHz. The core area of the chip occupies only 190 μm×530 μm in TSMC 40-nm CMOS process and consumes 28.2 mW.

关键词： Harmonic analysis Power harmonic filters Transistors Radio frequency Parasitic capacitance Capacitors Inductors

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Efficient and accurate neural field reconstruction using resistive memory

arXiv

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arXiv 2024年

作者： Yu, Yifei Wang, Shaocong Zhang, Woyu Zhang, Xinyuan Wu, Xiuzhe He, Yangu Yang, Jichang Zhang, Yue Lin, Ning Wang, Bo Chen, Xi Wang, Songqi Zhang, Xumeng Qi, Xiaojuan Wang, Zhongrui Shang, Dashan Liu, Qi Cheng, Kwang-Ting Liu, Ming Department of Electrical and Electronic Engineering The University of Hong Kong Hong Kong Hong Kong ACCESS – AI Chip Center for Emerging Smart Systems InnoHK Centers Hong Kong Science Park Hong Kong Hong Kong Institute of Mind The University of Hong Kong Hong Kong Hong Kong Key Lab of Fabrication Technologies for Integrated Circuits Institute of Microelectronics Chinese Academy of Sciences Beijing100029 China Laboratory of Microelectronic Devices and Integrated Technology Institute of Microelectronics Chinese Academy of Sciences Beijing100029 China University of Chinese Academy of Sciences Beijing100049 China Frontier Institute of Chip and System Fudan University Shanghai200433 China Department of Electronic and Computer Engineering The Hong Kong University of Science and Technology Hong Kong Hong Kong

Human beings construct perception of space by integrating sparse observations into massively interconnected synapses and neurons, offering a superior parallelism and efficiency. Replicating this capability in AI finds wide applications in medical imaging, AR/VR, and embodied AI, where input data is often sparse and computing resources are limited. However, traditional signal reconstruction methods on digital computers face both software and hardware challenges. On the software front, difficulties arise from storage inefficiencies in conventional explicit signal representation. Hardware obstacles include the von Neumann bottleneck, which limits data transfer between the CPU and memory, and the limitations of CMOS circuits in supporting parallel processing. We propose a systematic approach with software-hardware co-optimizations for signal reconstruction from sparse inputs. Software-wise, we employ neural field to implicitly represent signals via neural networks, which is further compressed using low-rank decomposition and structured pruning. Hardware-wise, we design a resistive memory-based computing-in-memory (CIM) platform, featuring a Gaussian Encoder (GE) and an MLP Processing Engine (PE). The GE harnesses the intrinsic stochasticity of resistive memory for efficient input encoding, while the PE achieves precise weight mapping through a Hardware-Aware Quantization (HAQ) circuit. We demonstrate the system’s efficacy on a 40nm 256Kb resistive memory-based in-memory computing macro, achieving 31.5×, 35.5×, and 47.2× energy efficiency improvements and 10.8×, 38.8×, and 6.2× parallelism improvements without compromising reconstruction quality in tasks like 3D CT sparse reconstruction, novel view synthesis, and novel view synthesis for dynamic scenes. This work advances the AI-driven signal restoration technology and paves the way for future efficient and robust medical AI and 3D vision applications. Copyright © 2024, The Authors. All rights reserved.

关键词： Signal reconstruction

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Tunable synaptic devices based on ambipolar MoTe2 transistor

Tunable synaptic devices based on ambipolar MoTe2 transistor

引用

IEEE Electron devices Technology and Manufacturing Conference (EDTM)

作者： Tingting Gao Xuefei Li Linxin Han Yanqing Wu Wuhan National High Magnetic Field Center and School of Optical and Electronic Information Huazhong University of Science and Technology Wuhan China Institute of Microelectronics and Key Laboratory of Microelectronic Devices and Circuits (MOE) Peking University Beijing China

Synapse is one of the main elements of hardware implementation in a neuron network. Complex CMOS technology-based circuits using various Si-based transistors, non-Si based memory devices like RRAM, and 2D FET devices serve as hardware implement for neuron network. In this work, we demonstrate ambipolar MoTe₂ FET devices with a wide range oftunability in synaptic characteristic and classical paired pulsed facilitation as well as spike-timing-dependent plasticity function.

关键词： Neurons Field effect transistors CMOS technology Hardware Biology Manufacturing Synapses

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