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International Conference on Solid-State and Integrated Circuit Technology

作者： Jin Luo Zhu Lv Qian-Qian Huang Cheng Chen Ru Huang Key Laboratory of Microelectronic Devices and Circuits (MOE) Institute of Microelectronics Peking University Beijing China

Compared with conventional tunneling field-effect transistor (TFET), the novel T-gate Schottky barrier TFET (TSB-TFET) with adaptive operation mechanism can effectively achieve higher I ON with dominant Schottky current, lower I OFF by introducing self-depleted effect and steep subthreshold slope with dominant band-to-band tunneling current. To facilitate the circuit simulation based on this new kind of device, in this paper, we establish a physical current model of TSB-TFET through modeling its modulated band-to-band tunneling and Schottky barrier injection current respectively. The current model results with different device parameters agree well with Sentaurus TCAD simulation results, showing its high applicability for further circuit design and simulation.

关键词： Junctions Schottky barriers Tunneling TFETs Logic gates Integrated circuit modeling Fingers

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Current Mirrors Based on Graphene Field-effect Transistors

Current Mirrors Based on Graphene Field-effect Transistors

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International Conference on Solid-State and Integrated Circuit Technology

作者： Pei Peng Zhongzhen Tian Muchan Li Zidong Wang Liming Reng Yunyi Fu Key Laboratory of Microelectronic Devices and Circuits (MOE) Institute of Microelectronics Peking University Beijing China

Current mirrors are significant elements in analog integrated circuits. Here, graphene-based field-effect transistors (GFETs) are fabricated and the parameters of device model for the fabricated GFETs are extracted from the measured I-V characteristics. The GFETs model was then coded with Verilog-A language for circuit simulation. Using simulation, we investigate the electrical properties of GFETs-based current mirrors. We found that in simple current mirror configuration, the output current is intensively dependent on the output voltage, and cannot track the reference current well. However, in GFETs-based cascode current mirror configuration, the output current can track the reference current in a proper range of output voltage, indicating the GFETs can implement cascode current mirrors. Furthermore, the GFETs-based cascode current mirror working as a load can efficiently improve the voltage gain of the GFETs-based amplifiers when compared to a resistor load.

关键词： Mirrors Graphene Integrated circuit modeling Logic gates Resistors Analytical models Current measurement

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Switching Dynamics and Computing Applications of Memristors:An Overview 12

Switching Dynamics and Computing Applications of Memristors:...

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2017 IEEE 12th International Conference on ASIC

作者： Qingxi Duan Teng Zhang Minghui Yin Caidie Cheng Liying Xu Yuchao Yang Ru Huang Key Laboratory of Microelectronic Devices and Circuits(MOE) Institute of MicroelectronicsPeking University

ISBN: (纸本)9781509066261;9781509066254

Memristors have acquired a lot of attention due to their potential applications in nonvolatile memory,reconfigurable logic,analog circuits and neuromorphic computing etc.,and important progress has been made *** we first shed light on the switching dynamics of oxide based memristors by electrostatic force microscopy(EFM).We further demonstrate a new type of vertical 3-terminal oxide based memristive device capable of implementing heterosynaptic *** address the long-standing issue of device variations in memristors limiting the construction of neuromorphic computing systems,we propose a fuzzy restricted Boltzmann machine(FRBM) network that can effectively tolerate device ***,we show that nonvolatile Boolean logic can also be achieved in the same 3-terminal heterosynaptic devices in an efficient manner,compared with conventional 2-terminal memristors.

关键词： memristors switching dynamics neuromorphic computing nonvolatile logic fuzzy restricted Boltzmann machine(FRBM) network

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Insight into multiple-triggering effect in DTSCRs for ESD protection

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Journal of Semiconductors 2017年第7期38卷 93-96页

作者： Lizhong Zhang Yuan Wang Yize Wang Yandong He Key Laboratory of Microelectronic Devices and Circuits (MoE) Institute of Microelectronics Peking UniversityBeijing 100871 China

The diode-triggered silicon-controlled rectifier（DTSCR） is widely used for electrostatic discharge（ESD） protection in advanced CMOS process owing to its advantages, such as design simplification, adjustable trigger/holding voltage, low parasitic capacitance. However, the multiple-triggering effect in the typical DTSCR device may cause undesirable larger overall trigger voltage, which results in a reduced ESD safe margin. In previous research, the major cause is attributed to the higher current level required in the intrinsic SCR. The related discussions indicate that it seems to result from the current division rule between the intrinsic and parasitic SCR formed in the triggering process. In this letter, inserting a large space into the trigger diodes is proposed to get a deeper insight into this issue. The triggering current is observed to be regularly reduced along with the increased space, which confirms that the current division is determined by the parasitic resistance distributed between the intrinsic and parasitic SCR paths. The theoretical analysis is well confirmed by device simulation and transmission line pulse（TLP） test results. The reduced overall trigger voltage is achieved in the modified DTSCR structures due to the comprehensive result of the parasitic resistance vs triggering current, which indicates a minimized multipletriggering effect.

关键词： electrostatic discharge（ESD） diode-triggered silicon-controlled rectifier（DTSCR） double snapback transmission line pulse（TLP） test

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BNReLU: Combine Batch Normalization and Rectified Linear Unit to Reduce Hardware Overhead

BNReLU: Combine Batch Normalization and Rectified Linear Uni...

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International Conference on ASIC

作者： Jiexian Ge Xiaoxin Cui Kanglin Xiao Chenglong Zou YiHsiang Chen Rongshan Wei College of Physics and Information Engineering Fuzhou University Fuzhou 350116 P. R. China Institute of Microelectronics Peking University Beijing P. R. China Key Laboratory of Microelectronics Devices and Circuits (MoE) Institute of Microelectronics Peking University Beijing P. R. China College of Physics and Information Engineering Fuzhou University Fuzhou P. R. China

With the pursuit of higher accuracy, the convolutional neural network has become deeper. Thus, the hardware overhead occupied have increased. Batch Normalization (BN) operation is an indispensable part of the network, and its occupied hardware resources cannot be ignored. In this paper, aiming to reduce hardware overhead caused by BN operation, we combine BN operation and ReLU activation function and propose the BNReLU operation without retraining the network. The experiment results show that compared with traditional BN+ReLU layer, hardware overhead of BNReLU operation is reduced by about 50%. With 32-bit float point input for each layer, the hardware overhead of BRAM, DSP, FF, and LUT for convolutional layer in the FPGA is reduced by 17.16%, 23.08%, 17.64%, and 16.05%.

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A 781Mbps-5Gbps DLL-Based CDR with Starting-Control Circuit

A 781Mbps-5Gbps DLL-Based CDR with Starting-Control Circuit

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IEEE International Conference on Solid-State and Integrated Circuit Technology

作者： Cheng Li Yuequan Liu Song Jia Yuan Wang Key Laboratory of Microelectronic Devices and Circuits (MoE) Institute of Microelectronics Peking University Beijing P. R. China

This paper presents a 781 Mbps-5 Gbps wide-range clock and data recovery (CDR) circuit combined delay-locked loop (DLL). A novel starting-control circuit is introduced to solve the inherent problem of false locking and expand the phase capture range. The phase detector (PD) achieves sampling and charge-pump tasks in one pass-gate construction, which optimizes the design complexity and cost. The results demonstrate the peak-to-peak jitter is 5.74 ps and the total power consumption is 4.6 mW at 4 Gbps with 1.2V power supply.

关键词： DLL-Based CDR PD

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A 1.9-kV/2.61-m${\text{m}}\Omega\cdot$ cm2 Lateral GaN Schottky Barrier Diode on Silicon Substrate With Tungsten Anode and Low Turn-ON Voltage of 0.35 V

IEEE Electron Device Letters

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IEEE Electron Device Letters 2018年第10期39卷 1548-1551页

作者： Tao Zhang Jincheng Zhang Hong Zhou Tangsheng Chen Kai Zhang Zhuangzhuang Hu Zhaoke Bian Kui Dang Yi Wang Li Zhang Jing Ning Peijun Ma Yue Hao Key Laboratory of Wide Band Gap Semiconductor Materials and Devices School of Microelectronics Xidian University Xi’an China Science and Technology on Monolithic Integrated Circuits and Modules Laboratory Nanjing Electronic Devices Institute Nanjing China

In this letter, we report the achievement of a high-performance lateral GaN Schottky barrier diode (SBD) on a silicon substrate with a low turn-ON voltage (V ON ) of 0.35 V and tungsten (W) as the anode. Non-field-plated lateral GaN SBDs with the anode-cathode distances (L AC ) of 6, 10, 15, 20, and 25 μm demonstrate the reverse breakdown voltages of 0.6, 1.1, 1.25, 1.5, and 1.9 kV with the differential specific ON-resistances (R ON , sp ) of 0.38, 0.72, 1.23, 1.87, and 2.61 mΩ·cm 2 , respectively. The power figure-of-merit (FOM) is calculated to be 1×10 3 , 1.7×10 3 , 1.3×10 3 , 1.2×10 3 , and 1.4×10 3 MW/cm 2 . To the best of our knowledge, this FOM of 1.7×10 3 MW/cm 2 is the highest among all the lateral GaN SBDs on a Si substrate. Combined with the ~10 8 current ON/OFF ratio at room temperature, the GaN SBD with the W anode shows a great promise for next-generation power electronics.

关键词： Gallium nitride Anodes Current density Silicon Wide band gap semiconductors Aluminum gallium nitride Schottky barriers

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A Self-Adaptive Digital Calibration Technique for MultiChannel High Resolution Capacitive SAR ADCs 12

A Self-Adaptive Digital Calibration Technique for MultiChann...

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2017 IEEE 12th International Conference on ASIC

作者： Binbin Lyu Wengao Lu Sijia Yang Zhongjian Chen Yacong Zhang Key Laboratory of Microelectronic Devices and Circuits Institute of MicroelectronicsPeking University Peking University Information Technology Institute(Tianjin Binhai)

ISBN: (纸本)9781509066261;9781509066254

This paper introduces a self-adaptive digital technique to calibrate multi-channel SAR *** than achieving higher resolution by adjusting the analog component values,this new digital method infers the capacitor weights of a SAR ADC with the help of a channel-shared high resolution sigma-delta ADC,which results in remarkable improvements in the capacitive SAR ADCs' *** increases from 11.06 bits to 12.67 *** digital calibration logic is based on LMS(least mean squares) and gradient descent.

关键词： SAR ADC multi-channel digital calibration

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Impact of Gate Asymmetry on Gate-All-Around Silicon Nanowire Transistor Parasitic Capacitance

Impact of Gate Asymmetry on Gate-All-Around Silicon Nanowire...

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International Conference on Solid-State and Integrated Circuit Technology

作者： Xiaoqiao Dong Yuancheng Yang Gong Chen Shuang Sun Qifeng Cai Xiaokang Li Xia An Xiaoyan Xu Wanrong Zhang Ming Li Faculty of Information Technology Beijing University of Technology Beijing China Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University Beijing China

In this paper, an analytical model is developed for parasitic gate capacitance of the gate-all-around (GAA) silicon nanowire MOSFETs (SNWT) with asymmetrical top and bottom gates. The modeling results show that the gate-to-source/drain spacer significantly impacts on the parasitic capacitance especially in the case of top-to-bottom gate misalignment. It is found that the optimized top-to-bottom gate misalignment may achieve smaller C p /C total so as to improve the AC performance of GAA SNWT. The developed capacitance model is more suitable for the actual process for further device design optimization.

关键词： Logic gates Parasitic capacitance Gallium arsenide Semiconductor device modeling MOSFET Silicon

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Design of a novel ternary SRAM sense amplifier using CNFET 12

Design of a novel ternary SRAM sense amplifier using CNFET

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12th IEEE International Conference on Advanced Semiconductor Integrated circuits, ASICON 2017

作者： Liu, Zizhao Pan, Tao Jia, Song Wang, Uan Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics EECS Peking University No.5 Yiheyuan Road Haidian District Beijing100871 China

ISBN: (纸本)9781509066247

This paper presents a novel design of a ternary SRAM sense amplifier using carbon nanotube field-effect transistors (CNFETs). Chirality of CNFET is used to control the threshold voltage to realize the ternary logic. Simulation results using HSPICE shows that the proposed SRAM sense amplifier perform correctly at 0.9V supply voltage in the ternary SRAM read process. And it can achieve 87.5% and 88.5% enhancement in speed, 84.2% and 85.6% in PDP, compared with a ternary DRAM sense amplifier and the ternary SRAM without sense amplifier. © 2017 IEEE.

关键词： Carbon nanotube field effect transistors

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