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检索条件"机构=Institute of Microelectronnics and Key Laboratory of Microelectronics Devices and Circuits"

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Statistical Analysis on Performance Degradation of 90 nm bulk SiMOS devices Irradiated by Heavy Ions 13

Statistical Analysis on Performance Degradation of 90 nm bul...

引用

2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT)

作者： Zhexuan Ren Xia An Weikang Wu Xing Zhang Ru Huang Key Laboratory of Microelectronic Devices and Circuits Institute of MicroelectronicsPeking University

ISBN: (纸本)9781467397209

In this paper, the radiation response of 90 nm bulk Si MOS devices irradiated by heavy ions is experimentally studied. Due to the intrinsic random incident of heavy ions, different performance degradation is observed, such as threshold voltage shift, saturation current change and maximum transconductance degradation. These performance degradations may be attributed to the displacement damage in channel region, interface states at gate oxide interface and trapped charges in STI, which are generated by heavy ion irradiation. Furthermore, the statistical analysis on the performance degradation of 90 nm bulk Si MOS devices is also demonstrated *** results indicate that the performance variation of90 nm bulk Si MOS devices enlarges after heavy ion irradiation compared with un-irradiated ***, the standard variation of threshold voltage shift, DIBL shift and off-state leakage current degradation induced by heavy ion irradiation increases with the decrease of gate width, which should be paid more attention. The results may provide guideline for radiation-hardened design.

关键词： Estimation Field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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Source/Drain Architecture Design of Vertical Channel Nanowire FET for 10nm and beyond 13

Source/Drain Architecture Design of Vertical Channel Nanowir...

引用

2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT)

作者： Gong Chen Ming Li Jiayang Zhang Yuancheng Yang Ru Huang Key Laboratory of Microelectronic Devices and Circuits Institute of MicroelectronicsPeking University

ISBN: (纸本)9781467397209

In this paper, a source/drain design for vertical channel nanowire FETs involving extension doping profile, spacer dielectric constant and spacer width is proposed and demonstrated by TCAD simulation. The results show that asymmetric graded lightly doped drain(AGLDD) exhibits very good SCE controllability and driving capability even with relatively large nanowire diameter. By adopting high-k spacer material and optimizing drain spacer width, preferable SCE immunity and higher overdrive current are achieved while parasitic capacitance can be maintained in an acceptable range. This scheme provides a feasible guideline for future low power vertical channel nanowire FETs design.

关键词： simulation FET Source/Drain Architecture Design of Vertical Channel Nanowire FET for 10nm and beyond

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Improved Crystallinity of Ultra-thin Amorphous Film By 2D-limited Regrowth: Process and Characterization 13

Improved Crystallinity of Ultra-thin Amorphous Film By 2D-li...

引用

2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT)

作者： Yuancheng Yang Ming Li Gong Chen Hao Zhang Xiaoyan Xu Ru Huang Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University

ISBN: (纸本)9781467397209

The 2-D limited regrowth of α-Si is proposed to achieve larger grain size and smoother surface simultaneously with conventional rapid thermal annealing process. Transmission line method is carried at room temperature and 100 K temperature separately to confirm that the boundary scattering and ionization scattering are possibly suppressed by the capping layer method due to less grain boundary and trapped ionization centers.

关键词： Monolithic 3D integration Amorphous silicon Two Dimensional(2D) Recrystallization Capping layer

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Nanoscale Ge Fin Etching Using Inductively Coupled Plasma for Ge-based Multi-gate devices 13

Nanoscale Ge Fin Etching Using Inductively Coupled Plasma fo...

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2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT)

作者： Bingxin Zhang Xia An Yuxuan Xia Ming Li Meng Lin Peilin Hao Xing Zhang Ru Huang Key Laboratory of Microelectronic Devices and Circuits Institute of MicroelectronicsPeking University

ISBN: (纸本)9781467397209

In this paper, nanoscale germanium(Ge) fin etching with inductively coupled plasma(ICP) equipment by Cl/BCl/Ar gas is experimentally demonstrated. The impact of Cl/BCl/Ar gas ratio on etching induced Ge surface roughness, etch rate, sidewall steepness, uniformity and layout dependence are comprehensively investigated. The surface roughness is improved by increasing Ar flow rate. A nearly vertical Ge Fin is obtained by optimizing Cl/BCl/Ar gas ratio. By using silicon oxide as hard mask, 60nm-width Ge Fin array with height of 100 nm is experimentally illustrated with high uniformity of etch depth and Fin width. Therefore, this method shows great potential for Ge-based multi-gate device fabrication.

关键词： Estimation Field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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A Hysteretic Buck DC-DC Converter Achieving 90% Peak Efficiency with Light-load Current of 0.1-10 mA 13

A Hysteretic Buck DC-DC Converter Achieving 90% Peak Efficie...

引用

2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT)

作者： Jiameng Qu Xiucheng Hao Fan Yang Junhua Liu Huailin Liao Key Laboratory of Microelectronic Devices and Circuits (MOE) Institute of Microelectronics Peking University

ISBN: (纸本)9781467397209

A buck DC-DC converter with very high light load efficiency is presented in this paper. It introduces hysteretic control when the large output ripple problem is not critical, especially in light-load condition. Moreover, a fast-response zero current detector(ZCD) is adopted to make the converter work in discontinuous conduction mode(DCM). Due to hysteretic control extremely simplified the control circuits, the converter is divided into two independent loops, which further simplifies the optimization of power consumption. The proposed converter is fabricated in a standard 55 nm CMOS process. It converts 1.8-2.5 V battery voltage into a stable output voltage of 1 V, and offers 100μA to 10 mA light-load current output. The hysteretic converter achieves peak efficiency of 88.5% and 90%, with a supply voltage of 2.5 V and 1.8 V, respectively.

关键词： DCM A Hysteretic Buck DC-DC Converter Achieving 90 Peak Efficiency with Light-load Current of 0.1-10 mA

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A Low Power Self-Turnoff Program Method for One-Time Programmable Memory 13

A Low Power Self-Turnoff Program Method for One-Time Program...

引用

2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT)

作者： Ling Shen Yongan Zheng Fan Yang Huailin Liao Yangyuan Wang Key Laboratory of Microelectronic Devices and Circuits (MOE) Institute of Microelectronics Peking University

ISBN: (纸本)9781467397209

A novel self-turnoff control circuit for program process of one-time programmable(OTP) cell is proposed. Utilizing the current turnoff technology after the breakdown of OTP cell, it lowers the power consumption efficiently compared with traditional structures without turnoff mechanism. In addition, an additional delay circuit is also attached to the self-turnoff circuit to ensure the complete breakdown of OTP cell. The simulation results show that the average power consumption of proposed circuit decreases to about 3nA in the whole program process.

关键词： OTP A Low Power Self-Turnoff Program Method for One-Time Programmable Memory

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A Low-Power and Small Chip-Area Fractional-N Digital PLL with Combination of DPI and TDC 13

A Low-Power and Small Chip-Area Fractional-N Digital PLL wit...

引用

2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT)

作者： Hangyan Guo Fan Yang Zherui Zhang Runhua Wang Junhua Liu Huailin Liao Key Laboratory of Microelectronic Devices and Circuits (MOE) Institute of Microelectronics Peking University

ISBN: (纸本)9781467397209

This paper presents a novel fractional-N digital PLL structure with a digitally controlled phase interpolator(DPI) and a time-to-digital converter(TDC). In this structure, a short bit-width DPI and a short bit-width TDC are combined to achieve high phase resolution and low in-band phase noise. Moreover, since the DPI readily achieves 360° phase range and the TDC provides good linearity, no extra complex calibration is needed, which simplifies the design and saves power and chip area. Designed in a 55-nm CMOS technology, the proposed digital PLL achieves-103 d Bc/Hz in-band phase noise at 2.4 GHz output frequency. It consumes 2.4 mW from a 1.2-V supply and occupies 0.18 mm2 active chip area.

关键词： A Low-Power and Small Chip-Area Fractional-N Digital PLL with Combination of DPI and TDC PLL

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A 7.9 fJ/conversion-step 10-bit 125 MS/s SAR ADC with Simplified Power-efficient Digital Control Logic 13

A 7.9 fJ/conversion-step 10-bit 125 MS/s SAR ADC with Simpli...

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2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT)

作者： Mingxiao He Fan Yang Xiucheng Hao Le Ye Huailin Liao Key Laboratory of Microelectronic Devices and Circuits (MOE) Institute of Microelectronics Peking University

ISBN: (纸本)9781467397209

This paper presents a 7.9 fJ /conversion-step 10-bit 125 MS/s successive approximation register(SAR) analog-to-digital converter(ADC) on the basis of a monotonic capacitor switching procedure. Simplified power-efficient digital control logic, multi-layer sandwich capacitor structure and high-speed level-shift bootstrapped sampling-and-holding(S/H) blocks are employed to achieve high performance with low power consumption. The prototype is implemented in 55 nm standard CMOS process, occupying an active area of 0.18 mm × 0.20 mm. Post simulation results show that an SNDR of 54.01 d B and an ENOB of 8.7 bit can be achieved by consuming 0.41 mW of the ADC core from a 1.2 V supply, and a figure of merit(FOM) of 7.9 fJ /conversion-step.

关键词： ADC SAR A 7.9 fJ/conversion-step 10-bit 125 MS/s SAR ADC with Simplified Power-efficient Digital Control Logic

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Multi-VT design of vertical channel nanowire FET for sub-10nm technology node 7

Multi-VT design of vertical channel nanowire FET for sub-10n...

引用

7th IEEE International Nanoelectronics Conference, INEC 2016

作者： Chen, Gong Li, Ming Fan, Jiewen Yang, Yuancheng Zhang, Hao Huang, Ru Key Laboratory of Microelectronic Devices Circuits Institute of Microelectronics Peking University Beijing China

ISBN: (纸本)9781467389693

In this work, a feasible multi-VT modulation strategy in vertical nanowire FETs (VNWFETs) combining asymmetric halo doping with nanowire diameter is proposed and verified by TCAD simulation. The results show that halo configuration close to source side exhibits larger VT-tuning range and better SCE controlling. Moreover, adjustment of halo doping concentration and nanowire diameters can be adopted to provide at least three VT choices for 7nm technology node. It is demonstrated that VNWFETs is quite promising for SOC application. © 2016 IEEE.

关键词： Nanowires

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Leakage Current Analysis Using High Resistivity Silicon Gated Diodes For PIN Detectors Application 13

Leakage Current Analysis Using High Resistivity Silicon Gate...

引用

2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT)

作者： Hao Wang Min Yu Baohua Shi Yahuan Huang Xinyang Zhao Yufeng Jin National Key Laboratory of Nano/Micro Fabrication Technology Key Laboratory of Microelectronic Devices and Circuits(MOE) Institute of Microelectronics Peking University

ISBN: (纸本)9781467397209

Ultra-thick and ultra-thin Silicon PIN detectors are specially applied in high particles detections. The corresponding leakage current is investigated. The ultra-thick and ultra-thin gated diodes structures based on high resistivity silicon substrates are fabricated and tested to analyses the reverse leakage current for silicon PIN detectors application. It is concluded that the contribution of the generation current in the main junction depletion region is more significant in the ultra-thick structures, while the contribution of the generation current generated at the silicon-oxide interface is more evident in the ultra-thin structures.

关键词： Leakage Current Analysis Using High Resistivity Silicon Gated Diodes For PIN Detectors Application PIN

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