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IEEE International Conference on Integrated Circuit Design and Technology (ICICDT)

作者： Pengpeng Ren Runsheng Wang Ru Huang Key Laboratory of Microelectronic Devices and Circuits (MOE) Institute of Microelectronics Peking University Beijing China

ISBN: (纸本)9781509003211

In this paper, the newly-found time-dependent layout dependent effects (LDE) due to layout dependency of device aging is presented. BTI and HCI degradation in nanoscale HKMG devices exhibits evident layout dependency, which will significantly complicate the circuit design. With the analysis on circuit level, the time-dependent LDE should be considered to ensure enough design margin, especially at end of life. This work is helpful to design-technology co-optimization at nanoscale nodes.

关键词： Layout Delays Aging Human computer interaction Degradation Nanoscale devices Reliability

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A novel low-power and high-speed dual-modulus prescaler based on extended true single-phase clock logic

A novel low-power and high-speed dual-modulus prescaler base...

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International Symposium on circuits and Systems

作者： Song Jia Ziyi Wang Zijin Li Yuan Wang Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University 100871 Beijing China

ISBN: (纸本)9781479953424

A novel low-power and high-speed dual-modulus prescaler based on extended true single-phase clock (E-TSPC) scheme is presented. By restricting the short-circuit current in noncritical branchs, the design reduces the major source of power dissipation in E-TSPC scheme. The presented design enhances the maximum working frequency with shorter critical path and lower load capacitances. Simulation results in SMIC 40nm process show that compared with referenced E-TSPC based designs at least 61.2% (divide-by-2) and 41.1% (divide-by-3) reduction in power delay product (PDP) can be achieved by the proposed design.

关键词： short-circuit power E-TSPC prescaler critical path

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A Combined Wafer Bonding Method using Spin-coated Water Glass Adhesive Layer and Spot Pressing Bonding Technique 13

A Combined Wafer Bonding Method using Spin-coated Water Glas...

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2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT)

作者： Yang Xu Shengkai Wang Yinghui Wang Dapeng Chen Honggang Liu Key Laboratory of Microelectronics Devices & Integrated Technology Institute of Micro Electronics of the Chinese Academy of Sciences Smart Sensing R&D Centre Institute of Micro Electronics of the Chinese Academy of Sciences High-Frequency High-Voltage Device and Integrated Circuits R&D Center Institute of Micro Electronics of the Chinese Academy of Sciences

A combined wafer bonding method consist of spot pressing bonding technique and water glass adhesive layer is proposed. The mechanism of water glass bonding is investigated, and the two major factors in this bonding me... 详细信息

ISBN: (纸本)9781467397209

关键词： wafer bonding water glass Spot Pressing Bonding surface energy voids formation

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A wafer-level characterization method of ESD protection circuits for both component-level and system-level applications

A wafer-level characterization method of ESD protection circ...

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Asia-Pacific Symposium on Electromagnetic Compatibility (APEMC)

作者： Yuan Wang Guangyi Lu Xing Zhang Key Laboratory of Microelectronic Devices and Circuits (MoE) Institute of Microelectronics Peking University Beijing P.R. China

Electrostatic discharge (ESD) protection circuits are often designed with detection circuits to trigger clamp devices to bypass ESD currents. In order to fully characterize performance of these protection circuits, a wafer-level characterization method is proposed in this work. By separating the detection rail from the supply rail, triggering actions resulted from detection circuits can be clearly captured by the proposed method. Besides, both the component-level triggering criteria and system-level transient-induced latch-up (TLU) immunity of ESD protection circuits can be fully characterized by the proposed method. Silicon-data based case studies are presented in this work to verify the validity of the proposed method.

关键词： Capacitance Levee

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Delay-locked loop based frequency quadrupler with wide operating range and fast locking characteristics

Delay-locked loop based frequency quadrupler with wide opera...

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International Symposium on circuits and Systems

作者： Yuan Wang Yuequan Liu Mengyin Jiang Song Jia Xing Zhang Key Laboratory of Microelectronic Devices and Circuits (MoE) Institute of Microelectronics Peking University 100871 Beijing P.R. China

ISBN: (纸本)9781479953424

A wide operating range and fast locking delay-locked loop (DLL) based frequency quadrupler that includes an eight-phase-clock generator and an edge combiner is proposed. The eight-phase-clock generator is composed of a coarse-code generator, a fine-code generator and a digital controlled delay line, which uses four differential delay units to generate equally spaced eight-phase clocks. The coarse-code generator adopts a time-to-digital scheme to achieve short locking time and wide operating range. A fine-code digital-to-analog converter in the fine-code generator converts the fine codes to analog voltage for high precision. Moreover, the novel edge-combiner circuit combines the eight-phase clocks to ×4 frequency output with 50% duty cycle ratio. Experimental results in a 65-nm CMOS process show this frequency multiplier can cover a frequency range from 320 MHz to 2.4 GHz and cost 5～40 cycles to finish locking.

关键词： fast locking quadrupler delay-locked loop (DLL) eight-phase-clock generator edge-combiner wide operating range

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A novel low-leakage power-rail ESD clamp circuit with adjustable triggering voltage and superior false-triggering immunity for nanoscale applications

A novel low-leakage power-rail ESD clamp circuit with adjust...

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International Symposium on circuits and Systems

作者： Guangyi Lu Yuan Wang Jian Cao Song Jia Xing Zhang Key Laboratory of Microelectronic Devices and Circuits (MoE) Institute of Microelectronics Peking University Beijing 100871 P.R. China

ISBN: (纸本)9781479953424

This work presents a novel power-rail electrostatic discharge (ESD) clamp circuit for nanoscale applications. By skillfully incorporating transient and static ESD detection mechanisms into its detection circuit, the proposed circuit achieves a wide range of adjustable triggering voltage (Ft1) while maintaining low standby leakage current (Ileak). Besides, the proposed circuit achieves significantly-improved false-triggering immunity compared with the transient-triggered circuit. All investigated circuits are fabricated in a 65-nm CMOS process. Simulation and test results have both confirmed the superiority of the proposed circuit. In addition, the proposed circuit achieves similar triggering behaviors in both transmission line pulsing (TLP) and very fast TLP (VF-TLP) tests.

关键词： transmission line pulsing (TLP) test Electrostatic discharge (ESD) detection circuit triggering voltage (Vt1) leakage current (Ileak)

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Heavy ion induced electrical property degradation in sub-100 nm bulk silicon MOS devices

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Journal of Semiconductors 2015年第11期36卷 30-33页

作者：陈叶华安霞武唯康张曜刘静静张兴黄如 Peking University Shenzhen Graduate School Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University School of Software and Microelectronics Peking University

The radiation response of 90 nm bulk silicon MOS devices after heavy ion irradiation is experimentally investigated. Due to the random strike of the incident particle, different degradation behaviors of bulk silicon MOS devices are observed. The drain current and maximum transconductance degrade as a result of the displacement damage in the channel induced by heavy ion strike. The off-state leakage current degradation and threshold voltage shift are also observed after heavy ion irradiation. The results suggest that the radiation induced damage of sub-100 nm MOS devices caused by heavy ion irradiation should be paid attention.

关键词： heavy ion displacement damage bulk silicon

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Effects of Si δ-Doping Condition and Growth Interruption on Electrical Properties of InP-Based High Electron Mobility Transistor Structures

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Chinese Physics Letters 2015年第9期32卷 112-115页

作者：周书星齐鸣艾立鹍徐安怀汪丽丹丁芃金智 State Key Laboratory of Functional Materials for lnformatics Shanghai Institute of Microsystem and Information Technology Chinese Academy of Sciences Shanghai 200050 Microveave Devices and Integrated Circuits Department Key Laboratory of Microelectronics Device and Integrated Technology Institute of Microelectronics Chinese Academy of Sciences Beijing 100029

The InGaAs/InAIAs/InP high electron mobility transistor （HEM：F） structures with lattice-matched and pseudo- morphic channels are grown by gas source molecular beam epitaxy. Effects of Si ^-doping condition and growth interruption on the electrical properties are investigated by changing the Si-cell temperature, doping time and growth process. It is found that the optimal Si ^-doping concentration （Nd） is about 5.0 x 1012 cm-2 and the use of growth interruption has a dramatic effect on the improvement of electrical properties. The material structure and crystal interface are analyzed by secondary ion mass spectroscopy and high resolution transmission elec- tron microscopy. An InGaAs/InAiAs/InP HEMT device with a gate length of lOOnm is fabricated. The device presents good pinch-off characteristics and the kink-effect of the device is trifling. In addition, the device exhibits fT = 249 GHa and fmax 〉 400 GHz.

关键词： InP InGaAs Doping Condition and Growth Interruption on Electrical Properties of InP-Based High Electron Mobility Transistor Structures Effects of Si

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Deep Insights into Dielectric Breakdown in Tunnel FETs with Awareness of Reliability and Performance Co-Optimization

Deep Insights into Dielectric Breakdown in Tunnel FETs with ...

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IEEE International Electron devices Meeting

作者： Qianqian Huang Rundong Jia Jiadi Zhu Zhu Lv Jiaxin Wang Cheng Chen Yang Zhao Runsheng Wang Weihai Bu Wenbo Wang Jin Kang Kelu Hua Hanming Wu Shaofeng Yu Yangyuan Wang Ru Huang Key Laboratory of Microelectronic Devices and Circuits (MOE) Institute of Microelectronics Peking University Beijing 100871 China Semiconductor Manufacturing International Corporation (SMIC) Shanghai 201203 and Beijing 100176 China

ISBN: (纸本)9781509039036

The gate dielectrics reliability in Tunnel FETs (TFETs) has been thoroughly investigated for the first time, which is found to be the dominant device failure mechanism compared with bias temperature ins tability degradation, and is much worse than MOSFETs with the same gate stacks due to a new stronger localized dielectric field peak at gate/source overlap region. The non-uniform electric field of dielectric in TFET also leads to the different mechanisms between soft breakdown and hard breakdown failure. Moreover, dielectric-field-associated parameters are discussed in detail, showing an intrinsic trade-off between dielectrics reliability and device performance optimization caused by the positive correlation between dielectric field and source junction field. A new robust design consideration is further proposed for reliability and performance co-optimization, which is experimentally realized by a new TFET design with both dramatically improved performance and reliability, indicating its great potentials for ultralow-power applications.

关键词： Tunnel FETs Awareness Reliability

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New Insights into the Near-Threshold Design in Nanoscale FinFET Technology for Sub-0.2V Applications

New Insights into the Near-Threshold Design in Nanoscale Fin...

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IEEE International Electron devices Meeting

作者： Xiaobo Jiang Shaofeng Guo Runsheng Wang Yuan Wang Xingsheng Wang Binjie Cheng Asen Asenov Ru Huang Key Laboratory of Microelectronic Devices and Circuits (MOE) Institute of Microelectronics Peking University Beijing 100871 China Synopsys 11 Somerset place Glasgow G3 7JT U.K

ISBN: (纸本)9781509039036

Energy consumption has become the major concern of the IC industry. As a result, near-threshold-voltage (NTV) design has attracted a lot of attention for its superiority in energy efficiency. However, NTV design is faced with the key challenge - variability, especially for FinFET technology where device electrical FoMs are found to be strongly correlated. In this paper, new methodology of NTV design optimization for FinFET is proposed for the first time, and demonstrated based on silicon data. Significant improvements are achieved in the following three aspects: (1) Our newly proposed predictive compact variability models in all-region are accurately calibrated with experimental data, using a simple characterization method;(2) A new efficient approach for logic design space optimization is proposed based on a set of elaborately selected subthreshold FoMs, and the impacts of variation on energy efficiency, delay variation and failure probability are thoroughly investigated;(3) The conventional gate sizing method is also ameliorated specifically for FinFET NTV design. Based on silicon data, the proposed methodology is then demonstrated under V~(dd)=199mV and V_(dd)=145mV, targeting energy-efficiency priority and V_(dd) priority scenarios, respectively. This work provides helpful guidelines for FinFET variation-aware near-threshold design.

关键词： New Insights into Near-Threshold Design FinFET

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