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International Electron devices Meeting (IEDM)

作者： Y. D. Zhao J. J. Hu P. Huang F. Yuan Y. Chai X. Y. Liu J. F. Kang Institute of Microelectronics Peking University Key Laboratory of Microelectronic Devices and Circuits (MOE) Peking University Innovation Center for MicroNanoelectronics and Integrated System Beijing China Department of Applied Physics The Hong Kong Polytechnic University Hong Kong China

ISBN: (纸本)9781509039036

A physics-based compact model is developed to capture the essential resistive switching behaviors of conductive-bridge random access memory (CBRAM) under DC and AC operations. Three types of evolution modes of conductive filament correlated with material properties and operation schemes are modeled based on experimental observations. By modeling the temperature and electric-field effects as well as the electrical conduction, the model can well reproduce the DC and AC switching characteristics in different material stacks and operation modes. The calibrated model can be further implemented into SPICE to evaluate and optimize the array performance of CBRAM as a device-circuit-system co-design tool.

关键词： Mathematical model Switches Metals Oxidation Geometry Electric fields Data models

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A Leakage Tolerant True Single-Phase Clock Dual-Modulus Prescaler Scheme

A Leakage Tolerant True Single-Phase Clock Dual-Modulus Pres...

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Asia-Pacific Microwave Conference

作者： Song Jia Ziyi Wang Shilin Yan Yuan Wang Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University

ISBN: (纸本)9781479987689

A new leakage-tolerant true single-phase clock dual-modulus prescaler based on a stage-merged scheme is presented. Leakage-restricting transistors are used to reduce the leakage currents at critical nodes and leakage-related malfunctions are eliminated at minimal cost in terms of speed, power and area overheads. An HSPICE simulation in a 40 nm process shows that the proposed divide-by-2/3 divider can effectively enhance robustness against leakage currents to extend the low frequency limit of the circuit over wide temperature and threshold voltage ranges. Additionally, the proposed design shows speed and power performance that is comparable to the performance levels of referenced designs.

关键词： Leakage currents Transistors Performance evaluation Clocks Phase locked loops Robustness Frequency conversion

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Effect of annealing on the characteristics of Ti/Al ohmic contacts to p-Type 4H-SiC

Effect of annealing on the characteristics of Ti/Al ohmic co...

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European Conference on Silicon Carbide & Related Materials (ECSCRM)

作者： Yi-Dan Tang Hua-Jun Shen Xu-Fang Zhang Guo Fei Bai Yun Zhao-Yang Peng Xin-Yu Liu High-Frequency High-Voltage Device and Integrated Circuits R&D Center Institute of Microelectronics of Chinese Academy of Sciences Beijing China School of Physical Science and Technology Lanzhou University Lanzhou China State Key Laboratory of Electronic Thin Films and Integrated Devices University of Electronic Science and Technology of china Chengdu China

Ti/Al contacts deposited on p-type epilayer doped with Al at 2×10 19 cm -3 are reported. The current-voltage curves of Ti/Al contacts annealed at different temperatures from 800 to 1000 °C were measured, which provided the specific contact resistances (SCRs) of 6.59×10 -5 Ω/cm 2 and 7.81×10 -5 Ω/cm 2 after annealing at 900°C for 5min and 950°C for 2min, respectively. The microstructures of Ti/Al contact on P-type 4H-SiC were investigated by X-ray diffraction (XRD). The results of XRD show that the phases of Ti 3 SiC 2 was formed at the metal/SiC interface after annealing, which could be effective to ohmic contacts on P-type 4H-SiC. The quantitative phase analysis were also discussed, which show that the phase composition of Ti 3 SiC 2 is key factor for low resistance to P-type 4H-SiC. Moreover, simulations proved that the gradual Ti 3 SiC 2 ISL reduces or eliminates the effective barrier height at the metal/Ti 3 SiC 2 /p-type and may also contribute to low contact resistivity.

关键词： Ohmic contacts Silicon carbide Annealing X-ray scattering Temperature measurement Microstructure Metals

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Fabricating GeO_2 passivation layer by N_2O plasma oxidation for Ge NMOSFETs application

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Chinese Physics B 2014年第6期23卷 538-541页

作者：林猛安霞黎明云全新李敏李志强刘朋强张兴黄如 Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University

In this paper, oxidation of Ge surface by N2O plasma is presented and experimentally demonstrated. Results show that 1.0-nm GeO2 is achieved after 120-s N20 plasma oxidation at 300 ℃. The GeO2/Ge interface is atomically smooth. The interface state density of Ge surface after N20 plasma passivation is about - 3 × 1011 ***-1. With GeO2 passivation, the hysteresis of metal-oxide-semiconductor （MOS） capacitor with A1203 serving as gate dielectric is reduced to - 50 mV, compared with - 130 mV of the untreated one. The Fermi-level at GeO2/Ge interface is unpinned, and the surface potential is effectively modulated by the gate voltage.

关键词： Ge GeO2 passivation N2O plasma oxidation Ge NMOSFETs

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Impacts of Dimensions, Number of Layers and Contact Structures on the Loss of Graphene-based Coplanar Waveguides through Simulations

Impacts of Dimensions, Number of Layers and Contact Structur...

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2015 IEEE 16th International Conference on Communication Technology(ICCT 2015)

作者： Qiaofeng Qin Zidong Wang Yuehui Jia Pei Peng Xin Gong Liming Ren Yunyi Fu Key Laboratory of Microelectronic Devices and Circuits (MOE) Institute of MicroelectronicsPeking University

We present modeling and simulations of graphene coplanar waveguide(GCPW) under the frequency up to 50 GHz. Our simulation results show that the dimensions of GCPW greatly influence its insertion loss. In addition, different graphene layer numbers and structures of graphene-metal contact were also considered. We show that the usage of few-layer graphene and end-contact structure is able to decrease the insertion loss, which helps improve the radio-frequency performance of graphene coplanar waveguide.

关键词： Graphene coplanar waveguide Simulation Insertion loss Few-layer graphene Contact structure

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A high frequency resolution digitally controlled oscillator with differential tapped inductor

A high frequency resolution digitally controlled oscillator ...

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IEEE International Symposium on circuits and Systems (ISCAS)

作者： Fan Yang Runhua Wang Xiaozhe Liu Junhua Liu Huailin Liao Key Laboratory of Microelectronic Devices and Circuits (MOE) Institute of Microelectronics Peking University Beijing China Key Laboratory of Microelectronic Devices and Circuits (MOE) Institute of Microelectronics Peking University Beijing Beijing CN

ISBN: (纸本)9781479983926

A novel architecture of high frequency resolution LC-tank based digitally controlled oscillator (DCO) is presented in this paper. The proposed architecture utilizes a differential tapped inductor and a capacitor array within the taps for fine frequency tuning. A prototype of 1.6 GHz DCO integrated in 0.18-μm CMOS technology exhibits a tuning range of 40.2% and a phase noise of -123.6 dBc/Hz@1MHz. With a minimal capacitance step of 7.5 fF, the frequency resolution is improved to 7.6 kHz/LSB. The DCO dissipates 3.2 mA from a 1.8 V supply and occupies an area of 0.46 mm 2 .

关键词： Inductors Capacitors Tuning Capacitance Arrays Phase noise

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A power efficient 1.0625–3.125 Gb/s serial transceiver in 130 nm digital CMOS for multi-standard applications

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Science China(Information Sciences) 2014年第6期57卷 182-191页

作者： HOU ZhongYuan YANG Fan LIU JunHua ZHANG Xing Key Laboratory of Microelectronic Devices and Circuits Institute of MicroelectronicsPeking University

A power-efficient and low-cost 1.0625–3.125 Gb/s serial transceiver is presented in this paper for Fiber Channel(FC),Peripheral Component Interconnect Express(PCIe),and RapidIO *** support multiple standards with a single low power and low cost design,the transceiver presented here uses a wide swing range source-series-terminated(SST)transmitter(TX),a passive receiver(RX)equalizer,a dual-loop phase locked loop(PLL)and a mixed signal clock and data recovery(CDR)*** proposed SST transmitter also realizes a 3bit 2-tap de-emphasis filter that compensates up to 6 dB on the transmitter,and a passive equalizer that achieves 4 dB transmission in the *** dual-loop PLL with an on-chip regulator is used to generate a low-jitter clock for the TX and CDR’s reference.A CDR with a phase interpolator(PI)is proposed with a mixed signal structure to recover the clock on the RX and it can tolerate a frequency offset of up to 2000 *** transceiver is fabricated in a 130 nm digital CMOS process and occupies an area of 0.8 *** supply voltages of 1.2 V and 3.3 V,the transceiver dissipates 78 mW when compensating for a total loss of 10 dB at3.125 Gb/s.

关键词： serial transceiver multi-standard power efficiency SST CDR

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Experimental clarification of orientation dependence of germanium PMOSFETs with Al_2O_3/GeO_x/Ge gate stack

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Chinese Physics B 2014年第11期23卷 626-629页

作者：云全新黎明安霞林猛刘朋强李志强张冰馨夏宇轩张浩张兴黄如王阳元 Key Laboratory of Microelectronic Devices and Circuits (MOE) Institute of MicroelectronicsPeking University

An extensive and complete experimental investigation with a full layout design of the channel direction was carried out for the first time to clarify the orientation dependence of germanium p-channel metal-oxide-semiconductor field-effect transistors （PMOSFETs）. By comparison of gate trans-conductance, drive current, and hole mobility, we found that the performance trend with the substrate orientation for Ge PMOSFET is （110）〉（111） ~ （100）, and the best channel direction is （110）/[110]. Moreover, the （110） device performance was found to be easily degraded as the channel direction got off from the [ 110] orientation, while （100） and （111） devices exhibited less channel orientation dependence. This experimental result shows good matching with the simulation reports to give a credible and significant guidance for Ge PMOSFET design.

关键词： germanium metal-oxide-semiconductor field-effect transistor orientation

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Impact of nitrogen plasma passivation on the interface of germanium MOS capacitor

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Chinese Physics B 2014年第11期23卷 616-619页

Nitrogen plasma passivation （NPP） on （111） germanium （Ge） was studied in terms of the interface trap density, roughness, and interfacial layer thickness using plasma-enhanced chemical vapor deposition （PECVD）. The results show that NPP not only reduces the interface states, but also improves the surface roughness of Ge, which is beneficial for suppressing the channel scattering at both low and high field regions of Ge MOSFETs. However, the interracial layer thickness is also increased by the NPP treatment, which will impact the equivalent oxide thickness （EOT） scaling and thus degrade the device performance gain from the improvement of the surface morphology and the interface passivation. To obtain better device performance of Ge MOSFETs, suppressing the interfacial layer regrowth as well as a trade-off with reducing the interface states and roughness should be considered carefully when using the NPP process.

关键词： germanium roughness interface trap density interfacial layer thickness

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A Low-Power High-Speed 32/33 Prescaler Based on Novel Divide-by-4/5 Unit with Improved True Single-Phase Clock Logic

A Low-Power High-Speed 32/33 Prescaler Based on Novel Divide...

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IEEE International Symposium on circuits and Systems

作者： Song Jia Shilin Yan Yuan Wang Ganggang Zhang Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University Beijing 100871 CHINA

ISBN: (纸本)9781479983926

In this work, new design techniques that aim to reduce power consumption of true single-phase clock-based (TSPC) prescalers is presented. The structure of divide-by-4/5 frequency divider is simplified, and its performance is compared with previous work to demonstrate the improvement. Simulation results show at least a 25% reduction of power consumption is achieved by the proposed unit. In the 32/33 dual modulus prescaler, a critical path cutting scheme is introduced to improve speed to the limit decided by the divide-by-4/5 unit.

关键词： TSPC prescaler frequency divider

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