The effect of the annealing time and annealing temperature on Ni/Ge/Au electrode contacts deposited on the n-type InP contact layer has been studied using a circular transmission line model. The minimum specific conta...
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The effect of the annealing time and annealing temperature on Ni/Ge/Au electrode contacts deposited on the n-type InP contact layer has been studied using a circular transmission line model. The minimum specific contact resistance of 3.210 7 cm2was achieved on the low-doped n-type InP contact layer with a 40 s anneal at 425 ℃. In order to improve the ohmic contact and reduce the difficulty in the fabrication of the high doped InP epi-layer, the doping concentration in the InP contact layer was chosen to be 51018cm 3in the fabrication of transferred electronic devices. Excellent differential negative resistance properties were obtained by an electron beam evaporating the Ni/Ge/Au/Ge/Ni/Au composite electrode on an InP epi-layer with a 60 s anneal at 380 ℃.
Formation and transfer of oxygen vacancies are essential to transitional metal oxide RRAM's switching behavior. In this paper, first principle is used to simulate the formation energy of oxygen vacancies in undope...
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With the process compatibility with the mainstream standard complementary metal-oxide-semiconductor (CMOS), shallow trench isolation (STI) based laterally diffused metal-oxide-semiconductor (LDMOS) devices have become...
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In this paper, passivation of Ge substrates by N2O plasma is proposed and compared with a N2 plasma treatment. Results show that both N2O and N2 plasma treatments can improve the quality of the interface between the h...
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The strain effect on the electronic properties of bilayer tungsten disulfide (WS2) is investigated by density functional theory (DFT). It is found that the band gap and carrier effective masses of AA and AB stacking b...
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Circuit reliability issues have great attention to the researchers, especially bias temperature instability (BTI). Obviously, the threshold voltage of the device degraded when the MOS is in the stress mode. For CMOS d...
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Nowadays, the strained-Si technology has been used to maintain the momentum of semiconductor scaling due to its enhancement performance result from the higher mobility. In this paper, the influence of ionizing impurit...
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An efficient test structure for interface trap density characterization has been proposed. Based on this single structure and one-time IV measurement, the interface trap densities on both n- and p-type Si/SiO 2 inter...
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ISBN:
(纸本)9781479932849
An efficient test structure for interface trap density characterization has been proposed. Based on this single structure and one-time IV measurement, the interface trap densities on both n- and p-type Si/SiO 2 interfaces are obtained, achieving 1x efficiency improvement and 50% cost reduction. BTI-stress-induced degradation was studied and compared under the same structure, demonstrating a better test efficiency and resolution to interface traps generation at different Si/SiO 2 interfaces.
The static BTI stress (DC stress) have a significant influence on duty cycle of Ring Oscillators, low power SRAMs and dynamic register files because of its asymmetrical gradation. A ring oscillator based structure is ...
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ISBN:
(纸本)9781479932849
The static BTI stress (DC stress) have a significant influence on duty cycle of Ring Oscillators, low power SRAMs and dynamic register files because of its asymmetrical gradation. A ring oscillator based structure is proposed to measure the duty cycle of an inverter chain based ring oscillator. The proposed structure can measure the duty cycle shifts conveniently and accurately. Simulating results shows that benefiting from the continuous accumulation, the duty-cycle of the inverter chain can be measured accurately.
Self-heating enhanced degradation in pLDMOSFETs was studied by non-destructive MR-DCIV method. Due to self-heating effect in pLDMOSFETs, several times larger MR-DCIV degradation per finger was observed for multi-finge...
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Self-heating enhanced degradation in pLDMOSFETs was studied by non-destructive MR-DCIV method. Due to self-heating effect in pLDMOSFETs, several times larger MR-DCIV degradation per finger was observed for multi-finger devices with higher temperature rise and less channel edge heat dissipation. Our study has shown that self-heating induced degradation shared the similar trends and mechanism to NBTI.
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