In the design of phase-change memory(PCM),it is important to perform numerical simulations to predict the performances of different device *** work presents a numerical simulation using a coupled system including Po...
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In the design of phase-change memory(PCM),it is important to perform numerical simulations to predict the performances of different device *** work presents a numerical simulation using a coupled system including Poisson's equation,the current continuity equation,the thermal conductivity equation,and phase-change dynamics to simulate the thermal and electric characteristics of phase-change *** method discriminates the common numerical simulation of PCM cells,from which it applies Possion's equation and current continuity equations instead of the Laplace equation to depict the electric characteristics of PCM cells,which is more adoptable for the semiconductor characteristics of phase-change *** results show that the simulation agrees with the measurement,and the scalability of PCM is predicted.
A high-performance PMOSFET based on silicon material of hybrid orientation is *** orientation wafers,integrated by(100) and(110) crystal orientation,are fabricated using silicon-silicon bonding, chemical mechanica...
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A high-performance PMOSFET based on silicon material of hybrid orientation is *** orientation wafers,integrated by(100) and(110) crystal orientation,are fabricated using silicon-silicon bonding, chemical mechanical polishing,etching silicon and non-selective expitaxy.A PMOSFET with W/L = 50μm/8μm is also processed,and the measured results show that the drain-source current and peak mobility of the PMOSFET are enhanced by up to 50.7%and 150%at V_(gs) =-15 V and V_(ds) =-0.5 V,*** mobility values are higher than that reported in the literature.
By way of periphery circuit design of the phase-change memory,it is necessary to present an accurate compact model of a phase-change memory cell for the circuit *** with the present model,the model presented in this w...
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By way of periphery circuit design of the phase-change memory,it is necessary to present an accurate compact model of a phase-change memory cell for the circuit *** with the present model,the model presented in this work includes an analytical conductivity model,which is deduced by means of the carrier transport theory instead of the fitting model based on the *** addition,this model includes an analytical temperature model based on the 1D heat-transfer equation and the phase-transition dynamic model based on the JMA equation to simulate the phase-change *** above models for phase-change memory are integrated by using Verilog-A language,and results show that this model is able to simulate theⅠ-Ⅴcharacteristics and the programming characteristics accurately.
In order to obtain power efficient flip-flops,two novel Hybrid-latch schemes are introduced in this paper. They achieve high performance by shortening the critical data path and power efficiency by eliminating the inv...
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ISBN:
(纸本)9781467324748
In order to obtain power efficient flip-flops,two novel Hybrid-latch schemes are introduced in this paper. They achieve high performance by shortening the critical data path and power efficiency by eliminating the inverter chain pulse *** simulation under SMIC 90nm process revealed that the two new flip-flop have excellent power and speed performance compared to the referenced *** can reduce 44.5% and 51.4% power dissipation,29.2% and 44.5% clock-to-output latency and 65.6% and 68.4% PDP.
RapidIO is a high-performance standard for embedded *** to different ending alignments of RapidIO packets,the corresponding CRC computations should be *** this paper,two selective parallel computation schemes based on...
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ISBN:
(纸本)9781467324748
RapidIO is a high-performance standard for embedded *** to different ending alignments of RapidIO packets,the corresponding CRC computations should be *** this paper,two selective parallel computation schemes based on simplified intermediate value equations are *** with the reference designs,the power dissipations can be reduced by more than 30% meanwhile better balances between the speeds and resource consumptions can be achieved.
In this paper,an enhanced Ge surface passivation method by nitrogen plasma immersion with adding RIE power is presented and experimentally demonstrated. With the acceleration effect resulting from electric field induc...
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In this paper,an enhanced Ge surface passivation method by nitrogen plasma immersion with adding RIE power is presented and experimentally demonstrated. With the acceleration effect resulting from electric field induced by proper RIE power,more nitrogen plasma will drift to Ge surface to passivate the dangling *** is shown that nitrogen plasma immersion with RIE power is efficient in suppressing Ge suboxide growth during high-K dielectric deposition,reducing interface states and improving the C-V characteristic of both p-MOS and n-MOS capacitors in terms of flat-band voltage and hysteresis.
The bias dependence of Channel Hot Carrier (CHC)degradation in 0.18μm SOI pMOSFETs is investigated in this *** classical bias modes (Vg@Isubmax and Vg=Vd)were applied to analyze the CHC degradation behavior of SOI **...
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ISBN:
(纸本)9781467324748
The bias dependence of Channel Hot Carrier (CHC)degradation in 0.18μm SOI pMOSFETs is investigated in this *** classical bias modes (Vg@Isubmax and Vg=Vd)were applied to analyze the CHC degradation behavior of SOI *** results show that at low Vg,hot carriers injection produced by impact ionization is the main factor contributed to ***,the degradation stressed at high Vg is controlled by both CHC and NBTI effect,showing the NBTI-like behavior at room temperature which indicates that NBTI effect is the dominant factor.A possible mechanism is put forward to explain the enhanced CHC degradation under Vg=Vd compared with pure NBTI *** influence of floating body on the performance degradation of PDSOI devices is also investigated.
The STI-based laterally diffused metal-oxide-semiconductor (LDMOS) devices have become popular with its better tradeoff between breakdown voltage and on-resistance and its compatibility with the standard complementary...
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The STI-based laterally diffused metal-oxide-semiconductor (LDMOS) devices have become popular with its better tradeoff between breakdown voltage and on-resistance and its compatibility with the standard complementary metal-oxide-semiconductor (CMOS) process. In this paper, a multi-region trap characterization direct current current-voltage (MR-DCIV) technique was proposed to characterize interface state generation in both channel and STI drift regions. The correlation between interface trap and MR-DCIV current has been verified by two-dimensional device simulation. Degradation of STI-based LDMOS transistors in various reliability stress modes is investigated experimentally by proposed technique. The impact of interface state location on device electrical characteristics is analyzed from measurement and simulation. Our study reveals that OFF-state stress becomes the worst degradation mode in term of the on-resistance degradation, which is attributed to interface state generation under STI drift region.
This paper describes a radiation detection readout circuit for portable dosimeter which is aimed at low power,low noise and high counting rate.A current feedback baseline holder circuit is proposed to solve the baseli...
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This paper describes a radiation detection readout circuit for portable dosimeter which is aimed at low power,low noise and high counting rate.A current feedback baseline holder circuit is proposed to solve the baseline shift problem without any other performance *** core circuit has been implemented in 0.35μm CMOS *** achieves 46mV/fC conversion gain,200kcps counting rate and consumes 260μA current from 3.3V *** no detector is connected to the chip,the equivalent input noise charge is 0.094fC rms.
The effect of CHF3 gas flow rate on the trench shape and etch rate was studied for germanium-based device *** this study,a sidewall tilt angle larger than 80°with the trench depth of 300nm was achieved by optimiz...
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The effect of CHF3 gas flow rate on the trench shape and etch rate was studied for germanium-based device *** this study,a sidewall tilt angle larger than 80°with the trench depth of 300nm was achieved by optimizing the flow rate ratio of SF6/CHF3/He gas ***,based on the experimental results,a Linear Reactive Ion Etching(RIE) Model was proposed to predict the optimized composition of the SF6/CHF3/He gas mixture to obtain steep trenches with low etch rate,which may provide the guideline for the germanium etching process design.
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