检索结果-内蒙古大学图书馆

2009 13th International Workshop on Computational Electronics, IWCE 2009

作者： Lang, Zeng Xiao, Yan Liu Gang, Du Jin, Feng Kang Ru, Qi Han Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University 100871 China

ISBN: (纸本)9781424439270

In this paper, we demonstrate a Monte Carlo simulator for ambipolar Schottky barrier MOSFETs which includes tunneling and thermal emission of electrons and holes and the appropriate treatment of carrier transport at nano-scale. The ambipolar characteristic of SB MOSFETs is reproduced by this simulator. The four operation modes in both n and p SB MOSFETs are revealed. Based on these simulations, it is summarized that the tunneling at source side dominates the carrier transport. ©2009 IEEE.

关键词： Schottky barrier diodes

来源：评论

学校读者我要写书评

暂无评论

Design of readout circuit for microcantilever infrared focal plane array with snapshot integration

Design of readout circuit for microcantilever infrared focal...

引用

International Symposium on Photoelectronic Detection and Imaging 2009: Advances in Infrared Imaging and Applications

作者： Lei, Ke Chen, Zhongjian Cao, Junmin Zhang, Yaciong Lu, Wengao Ji, Lijiu Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University 100871 China

ISBN: (纸本)9780819476647

Design of a CMOS readout circuit for 160x120 format microcantilever infrared FPAs with snapshot integration is presented in this paper. The pixel pitch is 50m and capacitive trans-impedance amplifier is used in pixel stage for low noise and high linearity. A 800fF storage capacitor is implemented in each pixel for snapshot imaging. The pixel OTAs are powered off during pixel signals readout phase and master-slave buffer method is employed in column readout stage and output buffer stage for low power. The 160x120 ROIC has been designed and simulated for 50Hz frame frequency with one output port. The pixel rate is 1MHz, charge handling capacity is 1.5x105 electrons, pixel linearity is as high as 99.9% and the power consumption is less than 20mw. A 16x16 experimental chip has been designed, post-simulated and manufactured with a 0.35m CMOS DPTM technology and is being tested. © 2009 SPIE.

关键词： Pixels

来源：评论

学校读者我要写书评

暂无评论

Investigation of Different Strain Configurations in Gate-All-Around Silicon Nanowire Transistor

引用

ECS Transactions 2010年第1期27卷

作者： Quanxin Yun Jing Zhuge Ru Huang Runsheng Wang Xia An Liangliang Zhang Xing Zhang Yangyuan Wang Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University NO.5 Yiheyuan Road Haidian District Beijing Beijing 100871 China Institute of Microelectronics Peking University

The impacts of three different strain configurations on both DC and RF performance of n-type silicon nanowire transistors (n-SNWTs) are investigated. It is found that the longitudinal tensile strain is the most efficient in improving the driving current and RF performance of n-SNWTs under the same stress value. In addition, the transverse compressive strain is also beneficial to the performance improvement, and can be combined in the stress engineering. Particularly, transverse biaxial compressive strain can effectively enhance the driving current, and at the same time slightly decrease the off-current of n-SNWT, which is beneficial for high speed and low power design. The results indicate that, due to the unique feature of gate-all-around 1D structure, the strain design in SNWTs, especially the combination of longitudinal strain and transverse strain, can be specially optimized for better device performance.

关键词：

来源：评论

学校读者我要写书评

暂无评论

A comparative study of double gate mosfet with asymmetric barrier heights at source/drain and the symmetric DG-SBFET

A comparative study of double gate mosfet with asymmetric ba...

引用

9th International Workshop on Junction Technology, IWJT 2009

作者： Du, Xiong-Xiong Sun, Lei Liu, Xiao-Yan Han, Ru-Qi Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University Beijing 100871 China

ISBN: (纸本)9781424439447

Double gate SBFET with asymmetric barrier heights at source/drain and the symmetric DG-SBFET are simulated. A comparative study between them is made. We have found that the DG-ASBFET is more appropriate for LOP and LSPT applications. Furthermore, the DG-ASBFET shows a better scale ability and better immunity to the short channel effects. ©2009 IEEE.

关键词： MOSFET devices

来源：评论

学校读者我要写书评

暂无评论

Design of readout circuit for microcantilever-based ripple uncooled infrared focal plane arrays

Design of readout circuit for microcantilever-based ripple u...

引用

International Symposium on Photoelectronic Detection and Imaging 2009: Advances in Infrared Imaging and Applications

作者： Cao, Junmin Chen, Zhongjian Lu, Wengao Zhang, Yacong Lei, Ke Zhao, Baoying Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University Beijing 100871 China

ISBN: (纸本)9780819476647

A readout integrated circuit (ROIC) for uncooled microcantilever infrared focal plane arrays (IRFPAs) based on capacitive readout is proposed. The ROIC is optimized according to noise modeling and analysis to reduce noise. An experimental chip of 1616 FPAs readout circuit has been designed and fabricated using 0.35um CMOS technology. The measurement results showed that the power dissipation is 16.5mW from a 5V supply voltage at 50Hz frame rate, the linearity is 99.2% at the typical mode;the uniformity is larger than 97% and the equivalent noise charge (ENC) is below 150e. It is believed that the ROIC has a great potential in the applications of large-scale micro-cantilever-based uncooled IRFPAs. © 2009 SPIE.

关键词： Timing circuits

来源：评论

学校读者我要写书评

暂无评论

Radial boundary forces-modulated valence band structure of Ge (110) nanowire

Radial boundary forces-modulated valence band structure of G...

引用

2009 13th International Workshop on Computational Electronics, IWCE 2009

作者： Honghua, Xu Yuhui, He Yuning, Zhao Gang, Du Jinfeng, Kang Ruqi, Han Xiaoyan, Liu Chun, Fan Institute of Microelectronics Key Laboratory of Microelectronic Devices and Circuits Peking University Beijing China Computer Center of Peking University Beijing China

ISBN: (纸本)9781424439270

For the radial boundary force induced in the process, the strain energy distribution and strain tensor components in Ge (110) nanowire (NW) are calculated by finite element method. Based on the strain distribution, we compute valence band structures with different radial forces. As increasing force values, top valence subbands shift downwards. The influence on the corresponding effective masses and density of states are also investigated. ©2009 IEEE.

关键词： Nanowires

来源：评论

学校读者我要写书评

暂无评论

Investigation of thermally robust single-component resistive switching organic memory cell

Investigation of thermally robust single-component resistive...

引用

67th Device Research Conference, DRC 2009

作者： Kuang, Yongbian Huang, Ru Wu, Dake Tang, Yu Yu, Zhe Ma, Ying Zhang, Lijie Tang, Poren Gao, Dejin Wen, Yongqiang Song, Yanlin Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University Beijing 100871 China Organic Solid Laboratory Institute of Chemistry Chinese Academy of Sciences Beijing 100080 China

ISBN: (纸本)9781424435289

A novel organic memory device based on titany 1 phthalocyanine (TiOPc) thin film sandwiched between Aluminum and indium tin oxide electrodes was reported. With a single-component organic material, the device can achieve good performance, such as a high on/off current ratio of 10 4, a large 4 V read voltage window, and good retention (14, 000s at 1 V stress). The organic memory cell can maintain bistable performance up to 525 K due to the thermal robustness of TiOPc, indicating the potential for hybrid integration with CMOS technology. The possible switching mechanis m is proposed and well fitted with experimental data. The results show that the interface is significant for the reversible switching phenomenon. Trap-filling space charge limited conduction (SCLC) with TiOPc charge confinement and electrochemical reaction at the interface inducing lower electron affinity can elucidate the switching behavior of the TiOPc memory cell. © 2009 IEEE.

关键词： Electron affinity

来源：评论

学校读者我要写书评

暂无评论

Zero skew clock synthesis in VLSI design

Zero skew clock synthesis in VLSI design

引用

Asia Pacific Conference on Postgraduate Research in microelectronics & Electronics (PrimeAsia)

作者： Guirong Wu Song Jia Yuan Wang Ganggang Zhang Key Laboratory of Microelectronics Devices and Circuits Institute of Microelectronics Peking University Beijing China

This paper proposes a ZSCTS methodology aiding in zero skew clock tree synthesis suitable to the mainstream industry clock tree synthesis (CTS) design flow. At the gate level, the original clock net is broken up into smaller partitions, and the clock buffers are inserted as pseudo clock sources to drive each portion. The automatic place and route (APR) tool may synthesize each clock subtree with better performance. The proposed methodology is applied to a chip level clock tree network and achieves good results.

关键词： Clocks Very large scale integration Decoding Energy consumption Pipelines Modems Production systems Degradation Accuracy Frequency

来源：评论

学校读者我要写书评

暂无评论

An efficient clock tree synthesis method in physical design

An efficient clock tree synthesis method in physical design

引用

IEEE Conference on Electron devices and Solid-State circuits

作者： Guirong Wu Song Jia Yuan Wang Ganggang Zhang Key Laboratory of Microelectronics Devices and Circuits Institute of Microelectronics Peking University Beijing China

This paper proposes a method aiding in low clock skew applicable to the mainstream industry clock tree synthesis (CTS) design flow. The original clock root is partitioned into several pseudo clock sources at the gate level. The automatic place and route (APR) tool may synthesize the clock tree with better performance in clock skew because each pseudo clock source drives smaller number of fan out. The proposed method is applied to a chip level clock tree network and achieves good results.

关键词： Clocks Design methodology Frequency synchronization Image edge detection Navigation Histograms Signal processing algorithms Frequency estimation Maximum likelihood detection Maximum likelihood estimation

来源：评论

学校读者我要写书评

暂无评论

Evaluation of Mobility in Graphene Nanoribbons Including Line Edge Roughness Scattering

Evaluation of Mobility in Graphene Nanoribbons Including Lin...

引用

International Conference on Simulation of Semiconductor Processes and devices (SISPAD)

作者： Lang Zeng Xiao Yan Liu Gang Du Jin Feng Kang Ru Qi Han Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University China

This work employs single particle Monte Carlo method to calculation the electron mobility in graphene nanoribbons including phonon scattering (acoustic and optical) and line edge roughness scattering. Mobility as high as 2 times 10 4 cm 2 /Vs is obtained and when the GNRs width is 2 nm, the mobility reduces to only about 200 cm 2 /Vs. These results agree well with experiment results. Also the effect of roughness parameters on mobility is analyzed.

关键词： Optical scattering Acoustic scattering Phonons Particle scattering Stimulated emission Electron mobility Electron optics Nanoscale devices microelectronics Monte Carlo methods

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：