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检索条件"机构=Institute of Microelectronnics and Key Laboratory of Microelectronics Devices and Circuits"

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Evaluation of Mobility in Graphene Nanoribbons Including Line Edge Roughness Scattering

Evaluation of Mobility in Graphene Nanoribbons Including Lin...

引用

International Conference on Simulation of Semiconductor Processes and devices (SISPAD)

作者： Lang Zeng Xiao Yan Liu Gang Du Jin Feng Kang Ru Qi Han Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University China

This work employs single particle Monte Carlo method to calculation the electron mobility in graphene nanoribbons including phonon scattering (acoustic and optical) and line edge roughness scattering. Mobility as high as 2 times 10 4 cm 2 /Vs is obtained and when the GNRs width is 2 nm, the mobility reduces to only about 200 cm 2 /Vs. These results agree well with experiment results. Also the effect of roughness parameters on mobility is analyzed.

关键词： Optical scattering Acoustic scattering Phonons Particle scattering Stimulated emission Electron mobility Electron optics Nanoscale devices microelectronics Monte Carlo methods

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A 16-bit 312.5-kHz bandwidth fourth-order one-bit switched-capacitor sigma-delta modulator

A 16-bit 312.5-kHz bandwidth fourth-order one-bit switched-c...

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IEEE Conference on Electron devices and Solid-State circuits

作者： Hongyi Li Yuan Wang Song Jia Xing Zhang Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University Beijing China

In this paper, a high-resolution medium-frequency single-loop fourth-order 1-bit sigma-delta modulator is implemented in 0.18 ¿m CMOS technology. The modulator has been presented with an oversampling ratio of 50, clock frequency of 31.25 MHz, 312.5 kHz bandwidth, and achieves a peak SNR of 101.7 dB, which is 16.6-bit resolution, 103 dB dynamic range. The whole circuits consume 58.55-mW from a single 1.8 V supply voltage. The experimental results show a figure-of-merit (FOM) of 170.27 dB. A system to circuit level design is finished in this paper.

关键词： Bandwidth Delta-sigma modulation Circuit topology CMOS technology Delta modulation Switches Signal resolution microelectronics Clocks Dynamic range

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A comparative study of double gate MOSFET with asymmetric barrier heights at source/drain and the symmetric DG-SBFET

A comparative study of double gate MOSFET with asymmetric ba...

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International Workshop on Junction Technology

作者： Xiong-Xiong Du Lei Sun Xiao-Yan Liu Ru-Qi Han Key Laboratory of Microelectronic Devices and Circuits Peking University Beijing P.R. China Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University Beijing 100871 China

Double gate SBFET with asymmetric barrier heights at source/drain and the symmetric DG-SBFET are simulated. A comparative study between them is made. We have found that the DG-ASBFET is more appropriate for LOP and LSPT applications. Furthermore, the DG-ASBFET shows a better scale ability and better immunity to the short channel effects.

关键词： MOSFET circuits Silicon Silicides microelectronics CMOS technology Semiconductor device doping Fabrication Schottky barriers Electrodes Electrons

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Investigation of thermally robust single-component resistive switching organic memory cell

Investigation of thermally robust single-component resistive...

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Device Research Conference

作者： Yongbian Kuang Ru Huang Dake Wu Yu Tang Zhe Yu Ying Ma Lijie Zhang Poren Tang Dejin Gao Yongqiang Wen Yanlin Song Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University Beijing P. R. China Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University Beijing China Organic Solid Laboratory Institute of Chemistry Chinese Academy of Sciences Beijing P. R. China

A novel organic memory device based on titanyl phthalocyanine (TiOPc) thin film sandwiched between Aluminum and indium tin oxide electrodes was reported. With a single-component organic material, the device can achieve good performance, such as a high on/off current ratio of 10 4 , a large 4 V read voltage window, and good retention (14,000 s at 1 V stress). The organic memory cell can maintain bistable performance up to 525 K due to the thermal robustness of Ti OPc, indicating the potential for hybrid integration with CMOS technology. The possible switching mechanism is proposed and well fitted with experimental data. The results show that the interface is significant for the reversible switching phenomenon. Trap-filling space charge limited conduction (S CLC) with TiOPc charge confinement and electrochemical reaction at the interface inducing lower electron affinity can elucidate the switching behavior of the TiOPc memory cell.

关键词： Thermal resistance Robustness CMOS technology Thin film devices Aluminum Indium tin oxide Electrodes Organic materials Voltage Thermal stresses

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Impact of Thickness and Deposition Temperature of Gate Dielectric on Valence Bands in Silicon Nanowires

Impact of Thickness and Deposition Temperature of Gate Diele...

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International Conference on Simulation of Semiconductor Processes and devices (SISPAD)

作者： Honghua Xu Yuhui He Chun Fan Yuning Zhao Gang Du Jinfeng Kang Ruqi Han Xiaoyan Liu Institute of Microelectronics Ministry of Education Peking University and Key Laboratory of Microelectronic Devices and Circuits Beijing China Computer Center Peking University Beijing China

The strain distribution and strained valence band structure in silicon nanowire with varied thicknesses and deposition temperatures of gate dielectric are discussed in detail in this work. Our calculation indicates that valence subbands are dependent on the structure and process parameters. Strain has little effects in (001) orientation. But in Si (110) nanowire, the valence subbands shift upper and warp remarkably as the gate dielectric becomes thicker. Taking thermal residual strain into consideration, the strained valence subbands go to higher energy positions compared to NW without the residual strain. The different deposition temperature by a certain process slightly influences the valence bands. Strain effects on densities of states and effective masses are also investigated.

关键词： Silicon Nanowires Capacitive sensors Dielectric devices Thermal expansion Tensile strain microelectronics Hafnium oxide Temperature distribution Effective mass

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Effects of Ionic Doping on the Behaviors of Oxygen Vacancies in HfO2 and ZrO2: A First Principles Study

Effects of Ionic Doping on the Behaviors of Oxygen Vacancies...

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International Conference on Simulation of Semiconductor Processes and devices (SISPAD)

作者： Haowei Zhang Bin Gao Shimeng Yu Lin Lai Lang Zeng Bing Sun Lifeng Liu Xiaoyan Liu Jing Lu Ruqi Han Jinfeng Kang Institute of Microelectronics Ministry of Education Peking University and Key Laboratory of Microelectronic Devices and Circuits Beijing China State Key Laboratory of Mesoscopic Physics and Department of Physics Peking University Beijing China

The effects of metallic ion (Al, Ti, or La) doping in HfO 2 or ZrO 2 on the behaviors of oxygen vacancies (V 0 ) such as the formation energy, density of states, and migration energy were investigated by using first principles calculations. The calculations show that, 1) the doping causes an upward shift of deep V 0 levels; 2) dopant radius has a weak impact on the relaxed formation energy of V 0 (E j v ) but a significant impact on the unrelaxed E f v ; 3) the relaxed formation energy E f v of V 0 is remarkably reduced by trivalent ion (Al or La) doping compared to by tetravalent ion (Ti) doping; 4) Al, Ti, or La doping impacts the migration barriers of V 0 along different directions.

关键词： Doping Oxygen Hafnium oxide microelectronics Laboratories Physics Zirconium High K dielectric materials High-K gate dielectrics Neural networks

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A unified FinFET reliability model including high K gate stack dynamic threshold voltage, hot carrier injection, and negative bias temperature instability

A unified FinFET reliability model including high K gate sta...

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IEEE International Symposium on Quality Electronic Design

作者： Chenyue Ma Bo Li Lining Zhang Jin He Xing Zhang Xinnan Lin Mansun Chan TSRC Key Laboratory of Microelectronic Devices and Circuits of Ministry of Education Institute of Microelectronics EECS Peking University Shenzhen China The Micro-& Nano Electronic Device and Integrated Technology Group The Key Laboratory of Integrated Microsystems Peking University Shenzhen China TSRC Key Laboratory of Microelectronic Devices and Circuits of Ministry of Education Institute of Microelectronics EECS Peking University Beijing China Peking University Beijing Beijing CN Department of ECE Hong Kong University of Science and Technology Hong Kong China

A unified FinFET reliability model including high K stack dynamic threshold (HKSDT), hot carrier injection (HCI), and negative bias temperature instability (NBTI) has been developed and verified by experimental data. The FinFET-based circuit performances are simulated and compared under these reliability issues by HSPICE simulator after the inclusion of the presented model.

关键词： FinFETs High K dielectric materials High-K gate dielectrics Threshold voltage Hot carrier injection Negative bias temperature instability Circuit simulation Human computer interaction Niobium compounds Titanium compounds

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Experimental investigation and design optimization guidelines of characteristic variability in silicon nanowire CMOS technology

Experimental investigation and design optimization guideline...

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International Electron devices Meeting (IEDM)

作者： Jing Zhuge Runsheng Wang Ru Huang Jibin Zou Xin Huang D.-W. Kim Donggun Park Xing Zhang Yangyuan Wang Institute of Microelectronics Peking University Beijing China Key Laboratory of Microelectronic Devices and Circuits Ministry of Education Beijing China Device Research Team Samsung Electronics Company Limited Kyunggi South Korea

ISBN: (纸本)9781424456390

In this paper, the characteristic variability in gate-all-around (GAA) silicon nanowire MOSFETs (SNWTs) is experimentally studied. Variation sources in SNWTs are extracted for the first time, taking into account the strongly-confined geometry induced quantum effect, quasi-ballistic effects, as well as the parasitic quantum resistance at the interface of 1D channel and 3D wide S/D regions. The measured results show that with suppressed random dopant fluctuations (RDF) in the intrinsic channel, variations in radius (R) and metal-gate work function (WF) of SNWTs dominate both the threshold voltage and on-current fluctuations, and line-edge-roughness (LER) shows minor impact. The influence of the SNWT variation sources on SRAM performance is estimated and compared with planar devices. In addition to process variation, variation induced by random telegraph signal (RTS) noise in SNWTs is also investigated for the evaluation of SRAM cell operating window. Design optimization guidelines are given based on the SRAM variation analyzed results.

关键词： CMOS technology Design optimization Guidelines Silicon Random access memory Fluctuations MOSFETs Geometry Electrical resistance measurement Resource description framework

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A novel calibration technique applying to an adaptive-bandwidth PLL

A novel calibration technique applying to an adaptive-bandwi...

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2008 9th International Conference on Solid-State and Integrated-Circuit Technology, ICSICT 2008

作者： Ying, Song Yuan, Wang Song, Jia Baoying, Zhao Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University 100871 China

ISBN: (纸本)9781424421855

This paper proposes a novel calibration technique and its application on an adaptive-bandwidth PLL. The new calibration method reduces calibration time by using an improved dual-edge phase detector to compare frequency difference directly. The maximum calibration time is less than five comparison periods. With the calibration technique and an adaptive bandwidth, the PLL can maintain optimal performance during the whole working range. The proposed circuit has been implemented in 0.18um CMOS logic process. Results show that the calibration time is less than 1.2s, and the total locking time is less than 3s. The PLL has good jitter performance within its operating range from 860MHz to 2.1GHz. © 2008 IEEE.

关键词： Phase locked loops

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A cost-efficient 12-bit 20Msamples/s pipelined ADC

A cost-efficient 12-bit 20Msamples/s pipelined ADC

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2008 9th International Conference on Solid-State and Integrated-Circuit Technology, ICSICT 2008

作者： Junmin, Cao Zhongjian, Chen Wengao, Lu Baoying, Zhao Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University 100871 China

ISBN: (纸本)9781424421855

A 12-bit 20MS/s cost-efficient pipelined analog-digital converter is presented. A dedicated first stage is proposed to eliminate the need of front-end SHA. Passive capacitor error-averaging technique (PCEA) and opamp sharing scheme are employed to achieve high resolutions and low power and area. The offset and 1/f noise of Opamp is reduced by interchanging the polarity of input and output of Opamp during different clock phases. Simulated with 0.5um CMOS technology, the ADC dissipates 65mw from a 5V supply, and achieves a peak SNDR of 70.1dB with a 1MHz full-scale sine input at 20MS/s. ©2008 IEEE.

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