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2008 9th International Conference on Solid-State and Integrated-Circuit Technology

作者： Song Ying Wang Yuan Jia Song Zhao Baoying Key Laboratory of Microelectronic Devices and Circuits Institute of MicroelectronicsPeking University

ISBN: (纸本)9781424421855

This paper proposes a novel calibration technique and its application on an adaptive-bandwidth *** new calibration method reduces calibration time by using an improved dual-edge phase detector to compare frequency difference *** maximum calibration time is less than five comparison *** the calibration technique and an adaptive bandwidth,the PLL can maintain optimal performance during the whole working *** proposed circuit has been implemented in 0.18um CMOS logic *** show that the calibration time is less than 1.2μs,and the total locking time is less than 3μ*** PLL has good jitter performance within its operating range from 860MHz to 2.1GHz.

关键词： PLL calibration low jitter

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A method to lower power in speed negotiation algorithm of fiber channel

A method to lower power in speed negotiation algorithm of fi...

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2008 9th International Conference on Solid-State and Integrated-Circuit Technology, ICSICT 2008

作者： Jin, Jie Yu, Dun Shan Cui, Xiao Xin Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University Beijing 100871 China

ISBN: (纸本)9781424421855

In this paper, we propose a simple but effective method to reduce the power in the design of the Speed Negotiation Algorithm(SNA). Based on thoroughly analyzing the algorithm and the results of simulation, we identify the large timers, the most commonly used in the SNA, as the most power consuming parts. This paper further develops a partition algorithm to tackle the power issue of the large timers. Utilizing the proposed method, we can reduce the power by 30% as opposed to only 19% if directly applying clock-gating methodology. Combined with clock-gating methodology, we can get 38% reduction in power with no more than 5% increase in area. © 2008 IEEE.

关键词： Clocks

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A low power high speed ROIC design for 10241024 IRFPA with novel readout stage

A low power high speed ROIC design for 10241024 IRFPA with n...

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2008 IEEE International Conference on Electron devices and Solid-State circuits, EDSSC

作者： Liu, Chang Lu, Wengao Chen, Zhongjian Bian, Haimei Ji, Lijiu Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University China

ISBN: (纸本)9781424425402

A low power high speed Read-Out Integrated Circuit (ROIC) for a short-wave Infra-Red Focal Plane Array (IRFPA) is designed as a prototype for 1024x1024 image system. Ripple integration and readout scheme as well as highly efficient power management are introduced to this design in order to decrease total power. To further increase the readout speed while decrease the power dissipation, a novel readout stage is proposed and adopted in this circuit. By using the new structure, the ROIC achieves a data rate of 10M/s per channel, with the total power dissipation of 56mW © 2008 IEEE.

关键词： Low power electronics

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Design and test results of a front-end ASIC for radiation detectors

Design and test results of a front-end ASIC for radiation de...

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2008 9th International Conference on Solid-State and Integrated-Circuit Technology, ICSICT 2008

作者： Yacong, Zhang Zhongjian, Chen Wengao, Lu Lijiu, Ji Zhao Baoying Key Laboratory of Microelectronic Devices and Circuits Institute Microelectronics Peking University 100871 China

ISBN: (纸本)9781424421855

A front-end ASIC for semiconductor radiation detectors is presented. It is composed of a Charge Sensitive Amplifier (CSA), a pulse shaper, and a Peak Detect and Hold (PDH) circuit. Poly-resistor is used as source degeneration component to reduce the noise of current source in the CSA. The ASIC has been designed in a 0.5um CMOS DPTM technology and tested with Verigy 93000. The gain (PDH excluded) is 78.5mV/fC and the Equivalent Noise Charge (ENC) with detector disconnected is 800-900e. The power dissipation without the output buffer is about 2.6mW. © 2008 IEEE.

关键词： Application specific integrated circuits

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A 900MHz UHF RFID reader transceiver in 0.18m CMOS technology

A 900MHz UHF RFID reader transceiver in 0.18m CMOS technolog...

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2008 9th International Conference on Solid-State and Integrated-Circuit Technology, ICSICT 2008

作者： Ye, Le Liao, Huailin Song, Fei Chen, Jiang Xiao, Huilin Liu, Ruiqiang Liu, Junhua Wang, Xinan Wang, Yangyuan Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University 100871 China

ISBN: (纸本)9781424421855

This paper presents a UHF band (840MHz-925MHz) RFID reader transceiver design for the protocols of EPC Class-1 Gen-2 and ISO/IEC 18000-6C. The architecture and modules for the proposed transceiver are described and implemented in a standard 0.18m CMOS process. To suppress the leakage signal from transmitter to receiver, directional coupler and leakage cancellation circuit are introduced in the transceiver. A mixer with common-gate capacitor-cross-coupled input stage and vertical NPN switching stage is introduced to satisfy wideband matching and reduce 1/f noise corner. The transceiver, with an on-chip Power-amplifier (PA) driver to drive off-chip PA, supports DSB-ASK, SSB-ASK and PR-ASK modulation schemes. A sigma-delta PLL is also implemented for 250kHz channel hopping. Measurement results are given. Mixer achieves -8dBm PldB and 6.25dB noise figure, phase noise of PLL is -127dBc/Hz @ 1MHz offset and settling time of channel hopping is within 30s. Settling time of killing leakage is less than 15 μs. The sensitivity of receiver can be -81dBm @ 40 kHz link frequency (LF). The total silicon area of the transceiver is 13mm2, and draws 75mA for 1.8V supply voltage. © 2008 IEEE.

关键词： Transceivers

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Design of low power and high performance explicit-pulsed flip-flops

Pan Tao Ti Hsueh Pao/Chinese Journal of Semiconductors

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Pan Tao Ti Hsueh Pao/Chinese Journal of Semiconductors 2008年第10期29卷 2064-2068页

作者： Zhang, Xiaoyang Jia, Song Wang, Yuan Zhang, Ganggang Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University Beijing 100871 China

The speed and delay of flip-flops are critical to the performance of digital circuit systems. Two novel structures for dual-edge triggered explicit-pulsed flip-flops are proposed in this paper. The charging and discharging times are greatly reduced due to the lower capacitance of the interval nodes in the new structures, and the short circuit power consumption is diminished by overcoming the race problem as well. The flip-flops are also superior to the structures reported in the literature in terms of both power dissipation and working speed.

关键词： Flip flop circuits

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3-D simulation of geometrical variations impact on nanoscale FinFETs

3-D simulation of geometrical variations impact on nanoscale...

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International Conference on Solid-State and Integrated Circuit Technology

作者： Shimeng Yu Yuning Zhao Yuncheng Song Gang Du Jinfeng Kang Ruqi Han Xiaoyan Liu Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University China Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University Guangdong China

ISBN: (纸本)9781424421855

Intra-die fluctuations in the nanoscale CMOS technology emerge inherently to geometrical variations such as line edge roughness (LER) and oxide thickness fluctuations (OTF). A full 3-D statistical simulation is presented to investigate the impact of geometrical variations on the FinFETs performance. In this work, roughness is introduced by a Fourier analysis of the power spectrum of Gaussian autocorrelation function. The influence of different geometrical variation sources is compared and summarized. The results shows that FinFETs performance is most sensitive to the fin LER, which causes a remarkable shift and fluctuations in threshold voltage, drain induced barrier lower effect (DIBL) and leakage current. The impact of gate LER follows that of fin LER. The simulation also suggests quantum confinement effect accounts for the aggressive fluctuations due to fin LER.

关键词： Solid modeling FinFETs Fluctuations CMOS technology Doping MOSFETs Autocorrelation Silicon Random sequences Circuit simulation

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Structure and Magnetic Properties of Co-doped TiO2 Nanotubes by Aqueous Solution Method

Structure and Magnetic Properties of Co-doped TiO2 Nanotubes...

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2008 9th International Conference on Solid-State and Integrated-Circuit Technology

作者： A-bo Zheng Yan Li Yi Wang Lei Sun Li-feng Liu De-dong Han Jin-feng Kang Xing Zhang Ru-qi Han Key Laboratory of Microelectronic Devices and Circuits Institute of MicroelectronicsPeking University

The Co-doped titanium dioxide nanotubes were synthesized via the aqueous solution *** hydrogenation,room temperature ferromagnetism (RTFM) was found in the cobalt doped titanium dioxide nanotubes at 300k by the vibrate sample magnetometer. As the concentration of cobalt increased,the observed ferromagnetism became *** X-ray diffraction, scanning electron microscopy,high-resolution transmission electron microscopy and energy dispersive X-ray spectroscopy were performed and excluded the existence of cobalt ***,the magnetic ions and oxygen vacancies induced by hydrogenation contribute to the observed ferromagnetism at 300K.

关键词： [IEEE keyword]Scanning electron microscopy Saturation magnetization Magnetic hysteresis Powders Titanium Cobalt Nanotubes

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Low Power Folding/Interpolating ADC with a Novel Dynamic Encoder Based on ROM Theory

Low Power Folding/Interpolating ADC with a Novel Dynamic Enc...

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2008 9th International Conference on Solid-State and Integrated-Circuit Technology

作者： Jilei Yin Yuan Wang Song Jia Zhen Liu Key Laboratory of Microelectronic Devices and Circuits Institute of MicroelectronicsPeking University

A 6-bit 200Msps Folding/Interpolating analog to digital converter(ADC) with a novel dynamic encoder based on Rom theory is *** Precharge & Evaluate dynamic circuit is employed in the novel encoder and the bit synchronization logic to achieve high speed and reduce power *** in SMIC 0.35um digital CMOS process,the whole ADC consumes only 35mW at a 3.3V voltage supply.

关键词： ADC MSB Low Power Folding/Interpolating ADC with a Novel Dynamic Encoder Based on ROM Theory

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Characteristics of sub-100nm Ferroelectric Field Effect Transistor with High-k Buffer Layer

Characteristics of sub-100nm Ferroelectric Field Effect Tran...

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2008 9th International Conference on Solid-State and Integrated-Circuit Technology

作者： Rui Jin Yuncheng Song Min Ji Honghua Xu Jinfeng Kang Ruqi Han Xiaoyan Liu Key Laboratory of Microelectronic Devices and Circuits Institute of MicroelectronicsPeking University

The simulation work is carried out using two dimension device simulator to investigate the characteristics of sub-100nm ferroelectric field effect transistor(FeFET) with high-k material as the buffer *** configurations of gate stack are simulated and *** is shown that the structure of double-layer buffer can improve the device performance *** important issues for FeFET scaling down are also discussed in this paper.

关键词： Buffer Characteristics of sub-100nm Ferroelectric Field Effect Transistor with High-k Buffer Layer

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