The simulation work is carried out using two dimension device simulator to investigate the characteristics of sub-100nm ferroelectric field effect transistor(FeFET) with high-k material as the buffer *** configuration...
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The simulation work is carried out using two dimension device simulator to investigate the characteristics of sub-100nm ferroelectric field effect transistor(FeFET) with high-k material as the buffer *** configurations of gate stack are simulated and *** is shown that the structure of double-layer buffer can improve the device performance *** important issues for FeFET scaling down are also discussed in this paper.
P-type Schottky barrier nanowire transistors （p-SB-NWTs） are computational studied in this paper. We analyzed the working principle and physical limits on their performance in *** impact of Schottky contact of SB-NW...
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P-type Schottky barrier nanowire transistors （p-SB-NWTs） are computational studied in this paper. We analyzed the working principle and physical limits on their performance in *** impact of Schottky contact of SB-NWTs on the current drivability,gate control and RF performance are studied comparing with conventional silicon nanowire transistors（SNWTs）.It is pointed out that the inferior performance of SB-NWTs can not be solved by changing the S/D or channel *** the other hand,small V_t,F_t and on-off ratio fluctuation caused by process variation on channel diameter are observed,which is an advantage of SB-NWTs.
A 12-bit 20MS/s cost-efficient pipelined analog-digital converter is presented.A dedicated first stage is proposed to eliminate the need of front-end SHA. Passive capacitor error-averaging technique(PCEA) and opamp sh...
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A 12-bit 20MS/s cost-efficient pipelined analog-digital converter is presented.A dedicated first stage is proposed to eliminate the need of front-end SHA. Passive capacitor error-averaging technique(PCEA) and opamp sharing scheme are employed to achieve high resolutions and low power and *** offset and 1/f noise of Opamp is reduced by interchanging the polarity of input and output of Opamp during different clock *** with 0.5um CMOS technology,the ADC dissipates 65mw from a 5V supply,and achieves a peak SNDR of 70.1dB with a 1MHz full-scale sine input at 20MS/s.
A low power Read-Out Integrated Circuit(ROIC) for a short-wave Infra-Red Focal Plane Array(IRFPA) is designed as a prototype for 1024×1024 image *** integration and readout scheme as well as highly efficient powe...
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A low power Read-Out Integrated Circuit(ROIC) for a short-wave Infra-Red Focal Plane Array(IRFPA) is designed as a prototype for 1024×1024 image *** integration and readout scheme as well as highly efficient power management is introduced to this design in order to decrease total power dissipation. To overcome the charge sharing problem caused by this low power readout scheme,novel low input capacitance column amplifier is *** Data rate is about 10M/s per channel,with a total power dissipation of 56mW.
A low power high speed Read-Out Integrated Circuit (ROIC) for a short-wave Infra-Red Focal Plane Array (IRFPA) is designed as a prototype for 1024 times 1024 image system. Ripple integration and readout scheme as well...
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A low power high speed Read-Out Integrated Circuit (ROIC) for a short-wave Infra-Red Focal Plane Array (IRFPA) is designed as a prototype for 1024 times 1024 image system. Ripple integration and readout scheme as well as highly efficient power management are introduced to this design in order to decrease total power. To further increase the readout speed while decrease the power dissipation, a novel readout stage is proposed and adopted in this circuit. By using the new structure, the ROIC achieves a data rate of 10 M/s per channel, with the total power dissipation of 56 mW.
This paper implements a sixteen-order high-speed Finite Impose Response(TTR) filter with four different popular methods:Conventional multiplications and additions;Full custom Distributed Arithmetic(DA) scheme;Add-and-...
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This paper implements a sixteen-order high-speed Finite Impose Response(TTR) filter with four different popular methods:Conventional multiplications and additions;Full custom Distributed Arithmetic(DA) scheme;Add-and-Shift method with advanced calculation *** scheme is analyzed in detail including implementing process and advantages and/or drawbacks in order to present a practical *** of these implementations are aimed to implement on Xilinx Spartan 3 devices and we also compare our results with an industry result produced by Xilinx CoregenTM also using Distributed *** premium add-and-shift method observes up to 80% reduction in total occupied slices and 63.3%versus the largest conventional parallel multiplication implementation.
The impact of gate misalignment on the performance of dopant-segregated Schottky Barrier MOSFET(DS SBTs) and on the carrier transport is investigated by Monte Carlo *** simulation results show that gate misalignment w...
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The impact of gate misalignment on the performance of dopant-segregated Schottky Barrier MOSFET(DS SBTs) and on the carrier transport is investigated by Monte Carlo *** simulation results show that gate misalignment with dopant-segregated structure(DSS) has less significant impact on drain current than that without *** influence of gate misalignment with DSS becomes notable only when drain voltage is high enough,while gate misalignment without DSS affects drain current always no matter how much drain voltage *** carrier transport,our results demonstrate that maximal velocity at source side of DS SBTs without gate misalignment shows saturation,while saturation doesn't exist in DS SBTs with gate misalignment.
This paper proposes a novel histogram BIST scheme for ADC static *** a monotonic ADC, the out codes have an approximate stair-like proportional relationship to the input *** on this property,a space decomposition tech...
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This paper proposes a novel histogram BIST scheme for ADC static *** a monotonic ADC, the out codes have an approximate stair-like proportional relationship to the input *** on this property,a space decomposition technique is proposed to reduce the testing *** utilizing this technique,ADC's static parameters can be estimated in shorter testing time with low hardware overhead. The availability of proposed histogram BIST scheme has been verified by simulation and the test results have been compared with those obtained from Verigy SOC 93000.
In this paper,we have focused our attention on DC characteristics degradation of 0.18μm MOSFETs after 10-MeV proton *** is shown that the threshold voltage shift,the transconductance degradation and the saturation dr...
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In this paper,we have focused our attention on DC characteristics degradation of 0.18μm MOSFETs after 10-MeV proton *** is shown that the threshold voltage shift,the transconductance degradation and the saturation drain current decrease are lager in PMOSFETs,while small effects are exhibited in *** the analysis,it is concluded that the basic damage mechanism is not ascribed to the gate oxide and the *** origin of the observed changes is due to the damage in spacer oxides of the *** mechanism involved is that the energetic protons incident on the spacer region lose their energy to displace the atoms, give rise to many defects,and create a disordered region(displacement damage region),where many defects and traps can capture positive charges to make the static characteristics ***,it is pointed out that the sidewalls are one of sensitive regions for irradiation hardness.
This paper presents a UHF band（840MHz25MHz） RFID reader transceiver design for the protocols of EPC Class-1 Gen-2 and ISO/IEC *** architecture and modules for the proposed transceiver are described and implemented i...
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This paper presents a UHF band（840MHz25MHz） RFID reader transceiver design for the protocols of EPC Class-1 Gen-2 and ISO/IEC *** architecture and modules for the proposed transceiver are described and implemented in a standard 0.18μm CMOS process. To suppress the leakage signal from transmitter to receiver,directional coupler and leakage cancellation circuit are introduced in the transceiver.A mixer with common-gate capacitor-cross-coupled input stage and vertical NPN switching stage is introduced to satisfy wideband matching and reduce 1/f noise *** transceiver,with an on-chip Power-amplifier（PA） driver to drive off-chip PA,supports DSB-ASK,SSB-ASK and PR-ASK modulation schemes.A sigma-delta PLL is also implemented for 250kHz channel *** results are *** achieves -8dBm P1dB and 6.25dB noise figure,phase noise of PLL is -127dBc/Hz @1MHz offset and settling time of channel hopping is within 30μ*** time of killing leakage is less than 15μ*** sensitivity of receiver can be -81dBm@40 kHz link frequency（LF）.The total silicon area of the transceiver is 13mnr,and draws 75mA for 1.8V supply voltage.
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