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检索条件"机构=Institute of Microelectronnics and Key Laboratory of Microelectronics Devices and Circuits"

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CMOS folding and interpolating ADC with a mixed-averaging distributed T/H circuit

CMOS folding and interpolating ADC with a mixed-averaging di...

引用

International Conference on Solid-State and Integrated Circuit Technology

作者： Zhen Liu Song Jia Yuan Wang Lijiu Ji Xing Zhang Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University China

ISBN: (纸本)9781424421855

An 8-bit 200 MHz low-power CMOS folding and interpolating analog-to-digital converter is presented. A novel mixed-averaging distributed T/H circuit is proposed to decrease the nonlinearity error of the ADC. The DNL/INL is 0.3/0.2 LSB according to MATLAB simulation results. This ADC is implemented in 0.5 um CMOS technology and the total power dissipation is merely 96 mW at a sampling rate of 200 MHz.

关键词： Sampling methods Power dissipation Switches Circuit simulation CMOS technology Synchronization Interpolation Clocks CMOS analog integrated circuits microelectronics

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A comprehensive study on Schottky barrier nanowire transistors (SB-NWTs): Principle, physical limits and parameter fluctuations

A comprehensive study on Schottky barrier nanowire transisto...

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International Conference on Solid-State and Integrated Circuit Technology

作者： Liangliang Zhang Zhaoyi Kang Runsheng Wang Ru Huang Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University China

ISBN: (纸本)9781424421855;9781424421862

P-type Schottky barrier nanowire transistors (p-SB-NWTs) are computational studied in this paper. We analyzed the working principle and physical limits on their performance in details. The impact of Schottky contact of SB-NWTs on the current drivability, gate control and RF performance are studied comparing with conventional silicon nanowire transistors (SNWTs). It is pointed out that the inferior performance of SB-NWTs can not be solved by changing the S/D or channel materials. On the other hand, small V t , F t and on-off ratio fluctuation caused by process variation on channel diameter are observed, which is an advantage of SB-NWTs.

关键词： Schottky barriers Fluctuations MOSFETs Silicon Tunneling Silicides Nanoscale devices microelectronics CMOS technology Contact resistance

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A novel linear histogram BIST for ADC

A novel linear histogram BIST for ADC

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International Conference on Solid-State and Integrated Circuit Technology

作者： Jianguo Ren Jianhua Feng Hongfei Ye Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University China

ISBN: (纸本)9781424421855

This paper proposes a novel histogram BIST scheme for ADC static testing. For a monotonic ADC, the out codes have an approximate stair-like proportional relationship to the input signal. Based on this property, a space decomposition technique is proposed to reduce the testing time. By utilizing this technique, ADC¿s static parameters can be estimated in shorter testing time with low hardware overhead. The availability of proposed histogram BIST scheme has been verified by simulation and the test results have been compared with those obtained from Verigy SOC 93000.

关键词： Histograms Built-in self-test Hardware microelectronics Laboratories Circuit testing Analytical models Parameter estimation Computational modeling Circuit faults

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The implementation methods of high speed FIR filter on FPGA

The implementation methods of high speed FIR filter on FPGA

引用

International Conference on Solid-State and Integrated Circuit Technology

作者： Ying Li Chungan Peng Dunshan Yu Xing Zhang Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University China

ISBN: (纸本)9781424421855

This paper implements a sixteen-order high-speed Finite Impose Response (FIR) filter with four different popular methods: Conventional multiplications and additions; Full custom Distributed Arithmetic (DA) scheme; Add-and-Shift method with advanced calculation schedule. Each scheme is analyzed in detail including implementing process and advantages and/or drawbacks in order to present a practical reference. All of these implementations are aimed to implement on Xilinx Spartan 3 devices and we also compare our results with an industry result produced by Xilinx CoregenTM also using Distributed Arithmetic. The premium add-and-shift method observes up to 80% reduction in total occupied slices and 63.3% versus the largest conventional parallel multiplication implementation.

关键词： Finite impulse response filter Field programmable gate arrays Arithmetic Job shop scheduling Digital signal processing microelectronics Energy consumption Programmable logic arrays Circuit synthesis Table lookup

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Novel structural Ti/Al-based ohmic contacts on AlGaN/GaN heterostructures

Novel structural Ti/Al-based ohmic contacts on AlGaN/GaN het...

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International Conference on Solid-State and Integrated Circuit Technology

作者： Zhihua Dong Jinyan Wang Min Yu Yilong Hao C. P. Wen Yangyuan Wang Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University China

ISBN: (纸本)9781424421855

To improve the performances of ohmic contacts for GaN devices, a novel multilayer Ti/Al-based metal scheme (Ti/Al/Ti/Al/Ti/Al/Ti/Al/Ni/Au) on undoped AlGaN/GaN heterostructures was employed. A contact with ¿c (specific contact resistance) of 8.74E-07 ¿·cm2, Rc of 0.22 ¿·mm was demonstrated. Ohmic contacts with the novel metal structure were measured with I-V, SEM, HRTEM to show their properties. The results showed that ohmic contacts with novel structures have better surface morphology and proposed thermal stability than those using conventional Ti/Al/Ni/Au metal scheme, therefore ohmic contacts with novel structures should be better candidates for high power and high frequency GaN devices.

关键词： Ohmic contacts Aluminum gallium nitride Gallium nitride Gold Nonhomogeneous media Contact resistance Electrical resistance measurement Surface morphology Surface resistance Thermal stability

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Theoretical study of low-energy electron penetration in resist-substrate target by Monte Carlo simulation

Theoretical study of low-energy electron penetration in resi...

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2008 9th International Conference on Solid-State and Integrated-Circuit Technology

作者： Liming Ren Baoqin Chen Ru Huang Xing Zhang Key Laboratory of Microelectronic Devices and Circuits Institute of MicroelectronicsPeking University Institute of Microelectronics of the Chinese Academy of Sciences

Low-energy electron beam lithography has a variety of *** traditional electron scattering model consisting of Rutherford elastic scattering cross section and Bethe continuous slowing down approximation formula are not suitable for low-energy electron beam lithography.A more accurate physical model describing the low-energy electron scattering processes was proposed in this *** Monte Carlo method was used to simulate the complex scattering processes of Gaussian-distribution low-energy electron beam in the target of thin film on thick *** simulation results show that low-energy electron beam lithographyhas advantages of high throughput,low proximity effects and small damage to the underlying *** is in agreement with the conclusion got from Lee et al's and Peterson et al's experiments.

关键词： Theoretical study of low-energy electron penetration in resist-substrate target by Monte Carlo simulation Carlo Monte

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A simple nano-scale patterning technology for FinFET fabrication

A simple nano-scale patterning technology for FinFET fabrica...

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International Conference on Solid-State and Integrated Circuit Technology

作者： Xu Han Chengen Yang Dingyu Li Shengdong Zhang Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University Beijing China

ISBN: (纸本)9781424421855;9781424421862

In this paper, a simple low-cost sub-50 nm silicon fin patterning technology is proposed and experimentally demonstrated. The technology is based on a micro-meter level lithography equipment, that is, it does not need any critical photolithographic step. The masking layer for fin formation is the nitride caped oxide layer which is reduced in width from sub-micrometer scale to nano-meter scale through a lateral etching in BOE. The etching rate is shown to slow down as the etching process goes on. A nano-scale oxide hard mask can be achieved after the nitride is removal. Both the cross-sectional view and top view of the etching process are shown by SEM photographs. Results indicate the simple patterning way is of low cost and under good control, and applicable to FinFET technology.

关键词： FinFETs Fabrication Etching Lithography Silicon Nanoscale devices microelectronics circuits Electron beams Ultraviolet sources

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A method to lower power in speed negotiation algorithm of fiber channel

A method to lower power in speed negotiation algorithm of fi...

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International Conference on Solid-State and Integrated Circuit Technology

作者： Jie Jin Dun Shan Xiao Xin Cui Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University Beijing China Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University Beijing P. R. China

ISBN: (纸本)9781424421855

In this paper, we propose a simple but effective method to reduce the power in the design of the speed negotiation algorithm(SNA). Based on thoroughly analyzing the algorithm and the results of simulation, we identify the large timers, the most commonly used in the SNA, as the most power consuming parts. This paper further develops a partition algorithm to tackle the power issue of the large timers. Utilizing the proposed method, we can reduce the power by 30% as opposed to only 19% if directly applying clock-gating methodology. Combined with clock-gating methodology, we can get 38% reduction in power with no more than 5% increase in area.

关键词： Analytical models Partitioning algorithms Clocks CMOS technology Storage area networks microelectronics Algorithm design and analysis Automata Optical fiber devices Laboratories

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Investigations on proton-irradiation-induced spacer damage in deep-submicron MOSFETs

Investigations on proton-irradiation-induced spacer damage i...

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International Conference on Solid-State and Integrated Circuit Technology

作者： Shoubin Xue Pengfei Wang Ru Huang Dake Wu Yunpeng Pei Wenhua Wang Xing Zhang Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University Beijing China

ISBN: (纸本)9781424421855;9781424421862

In this paper, we have focused our attention on DC characteristics degradation of 0.18 ¿m MOSFETs after 10-MeV proton irradiation. It is shown that the threshold voltage shift, the transconductance degradation and the saturation drain current decrease are lager in PMOSFETs, while small effects are exhibited in NMOSFETs. From the analysis, it is concluded that the basic damage mechanism is not ascribed to the gate oxide and the isolation. The origin of the observed changes is due to the damage in spacer oxides of the MOSFETs. The mechanism involved is that the energetic protons incident on the spacer region lose their energy to displace the atoms, give rise to many defects, and create a disordered region (displacement damage region), where many defects and traps can capture positive charges to make the static characteristics degraded. Therefore, it is pointed out that the sidewalls are one of sensitive regions for irradiation hardness.

关键词： MOSFETs Protons Degradation Voltage CMOS technology Dielectric breakdown microelectronics Space technology Laboratories circuits

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Characteristics of sub-100nm ferroelectric field effect transistor with high-k buffer layer

Characteristics of sub-100nm ferroelectric field effect tran...

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International Conference on Solid-State and Integrated Circuit Technology

作者： Rui Jin Yuncheng Song Min Ji Honghua Xu Jinfeng Kang Ruqi Han Xiaoyan Liu Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University Beijing China

ISBN: (纸本)9781424421855

The simulation work is carried out using two dimension device simulator to investigate the characteristics of sub-100 nm ferroelectric field effect transistor (FeFET) with high-k material as the buffer layer. Different configurations of gate stack are simulated and analyzed. It is shown that the structure of double-layer buffer can improve the device performance efficiently. Some important issues for FeFET scaling down are also discussed in this paper.

关键词： Ferroelectric materials FETs High K dielectric materials High-K gate dielectrics Buffer layers Polarization Threshold voltage Circuit simulation Capacitors Semiconductor process modeling

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