We propose the formal model of programming language constraints, which allows specifying stylistic, syntax and contextual rules. We also give the classification of those constraints. We describe the developed program ...
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ISBN:
(纸本)9781479957910
We propose the formal model of programming language constraints, which allows specifying stylistic, syntax and contextual rules. We also give the classification of those constraints. We describe the developed program model and the set of static analysis algorithms for the analyzer subsystem that implements automatic constraints checking and describe the implementation of the proposed formalizations in the Clang open source compiler.
The Problem of the Unknown Component: Theory and Applications addresses the issue of designing a component that, combined with a known part of a system, conforms to an overall specification. The authors tackle this pr...
ISBN:
(纸本)9781489973948
The Problem of the Unknown Component: Theory and Applications addresses the issue of designing a component that, combined with a known part of a system, conforms to an overall specification. The authors tackle this problem by solving abstract equations over a language. The most general solutions are studied when both synchronous and parallel composition operators are used. The abstract equations are specialized to languages associated with important classes of automata used for modeling systems. The book is a blend of theory and practice, which includes a description of a software package with applications to sequential synthesis of finite state machines. Specific topologies interconnecting the components, exact and heuristic techniques, and optimization scenarios are studied. Finally the scope is enlarged to domains like testing, supervisory control, game theory and synthesis for special omega languages. The authors present original results of the authors along with an overview of existing ones.
By 1991, several copies of two vector-pipeline supercomputers: “Electronica SSBIS” (the development of the Research institute “Delta”, MEI USSR and the institute of Cybernetics, AS USSR - chief designer Vladimir A...
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By 1991, several copies of two vector-pipeline supercomputers: “Electronica SSBIS” (the development of the Research institute “Delta”, MEI USSR and the institute of Cybernetics, AS USSR - chief designer Vladimir Andreevich Melnikov), and “modular pipelined processor (MPP)” (the development of the Lebedev institute of Precision mechanics and Computer Engineering - Chief Designer Andrei Andreevich Sokolov) have been designed and produced.
This paper considers an algorithm for scalable automatic static analysis to detect defects in programs written in C. We propose a criterion for emitting warnings based on reachability of function statements. Main adva...
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This paper considers an algorithm for scalable automatic static analysis to detect defects in programs written in C. We propose a criterion for emitting warnings based on reachability of function statements. Main advantages of the proposed approach are scalability, high true positive rate and ability to perform library analysis.
system-on-Chip architectures are increasingly designed for safety-related purposes. As a very high level of interlocking of hard- and software is required for such specialized systems, different concepts for the softw...
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system-on-Chip architectures are increasingly designed for safety-related purposes. As a very high level of interlocking of hard- and software is required for such specialized systems, different concepts for the software composition are necessary. This paper investigates the benefits resulting from the utilization of a middleware which handles all low-level hardware access demanded by the application. Several measures recommended by standard IEC 61508 are implemented “quasi-automatically” if a certified middleware is used. In addition, the certification effort is drastically decreased if the implementation of main functionalities is based on certified, reused components. Another “side-effect” is the hiding of details concerning the system-on-chip and the operating system as the application always uses the middleware interfaces.
Due to the continuing development of semiconductor structures, it can be allowed nowadays to integrate faster and more efficient systems into a very small area of silicon. In such system-on-chip, all individual compon...
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Due to the continuing development of semiconductor structures, it can be allowed nowadays to integrate faster and more efficient systems into a very small area of silicon. In such system-on-chip, all individual components of a target control system can be integrated into a single silicon die at lowest level, which in turn contributes in saving the substantial space and reduces power consumption and production costs. With the consideration of the miniaturization of safety-related systems into system-on-chips, where usually complete redundant architectures along with memories and interfaces are integrated into small silicon structures, many advantages can be taken into account. These advantages extend to all levels of the development cycle. In the present paper, a concept for on-chip safety system architecture is presented briefly. Primarily, a qualitative evaluation and analysis of the presented architecture is explicitly focused and discussed. The evaluation and analysis is based on a comparison to a similar conventional discrete safety-related architecture.
Since the advent of traditional random access memory (RAM) tests, such as Checkerboard, more sophisticated tests and fault models have evolved, taking the characteristics of memories into account. Thus, given a specif...
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Since the advent of traditional random access memory (RAM) tests, such as Checkerboard, more sophisticated tests and fault models have evolved, taking the characteristics of memories into account. Thus, given a specific type of memory, it would be straightforward to determine suitable state-of-the-art tests. However, the question our research focuses on is: “Which RAM tests do not need to be performed due to the safety architecture?” Even high-performance tests do require execution time. In the range of safety-related systems, diagnostics may consume most of the central processing unit (CPU) time, depending on the architecture. Therefore, this paper depicts how architectural characteristics can be taken into account to reasonably simplify specific RAM tests. This paper introduces our research on RAM tests in the range of safety-related systems. Therefore, key topics are introduced, first: comprehensively and starting from scratch, thus enabling anyone to follow our research. Second, an example is shown on how detecting stuck-at faults of address and data words, as demanded by IEC 61508 Ed.2.0, can be simplified by taking advantage of a 1oo2D safety architecture.
With the release of the second edition of the standard IEC 61508 for functional safety of electrical, electronic and programmable electronic systems, a set of methodologies and implementation techniques was presented,...
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With the release of the second edition of the standard IEC 61508 for functional safety of electrical, electronic and programmable electronic systems, a set of methodologies and implementation techniques was presented, which allows the realization and certification of safety-related solutions with on-chip redundancy. In a broader context, the standard ISO 26262 offers similar methodologies for safety solutions for automotive applications. The main focus of the research work of our institute is laid on the development and certification of safety-chips according to the standard IEC 61508. Together with an industrial partner, we are developing chip-based safety-related solutions for several industrial applications. In the same context, several semiconductor manufacturers addressed the development of such solutions in the last years, mainly with the focus on automotive applications. The present paper provides an overview of existing and planned safety chip architectures. Furthermore, a cursory analysis of the presented safety-chips is carried out with respect to the standard IEC 61508. A deep qualitative and quantitative analysis require experiments and simulations which will be carried out in future work.
Many state machine based strategies return complete but infinite test suites. A usual approach to guarantee the fault coverage with respect to some kind of faults is to limit the number of faults, i.e., to consider a ...
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Many state machine based strategies return complete but infinite test suites. A usual approach to guarantee the fault coverage with respect to some kind of faults is to limit the number of faults, i.e., to consider a finite fault domain. In this paper, we summarize some results on deriving complete test suites w.r.t. infinite faults domains but w.r.t. special types of the specification machine.
In paper shortly describes handling calculable complex "Dnepr-2, which including a calculable machine "Dnepr-21" and handling machine "Dnepr-22" for the management by Technologies Processes (T...
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In paper shortly describes handling calculable complex "Dnepr-2, which including a calculable machine "Dnepr-21" and handling machine "Dnepr-22" for the management by Technologies Processes (TP) objects to Automatisation systems. Complex"Dnepr-2" was elaborated in institute of cybernetics AN Ukraine and his special designer bureau of mathematical machines and systems under the direction of the academician V.M. Gluchkov (Decision of CM USSR No 1250 from 12.12.1965). This complex was one of pioneer works in USSR. In him on period of 60 years of past century new and original scientific and technical decisions are realized. In complex "Dnepr-2" was realized management by the calculation and treatment in real time by objects, system of breaking, operation system with the division of time, translators from the new languages (Auto cod, Algol-60, COBOL and others).
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