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2011 9th East-West Design and Test Symposium, EWDTS'2011

作者： Kamkin, Alexander Institute for System Programming Russian Academy of Sciences A. Solzhenitsyn st. 25 109004 Moscow Russia

ISBN: (纸本)9781457719578

Simulation-based verification is a widely-spread approach to ensure functional correctness of hardware designs [1,2]. It is usually done by co-simulating a design under verification with an independently created reference model and checking conformance of their reactions. To reduce verification expenses, abstract models are commonly used (they are simpler, less error-prone and more reusable). Design timing (decomposition of operations into micro-operations and scheduling of those micro-operations) is the main object for abstraction. However, there are several problems in using time-abstract reference models for simulation-based verification. The paper discusses some of the problems and suggests simple, practice-oriented techniques to solve them. © 2011 IEEE.

关键词： Adaptation models Data communication Data models Delay Encyclopedias Hardware Synchronization conformance checking conformance testing formal verification hardware design practice oriented technique reference model simulation based hardware verification t

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Sophisticated Calculation of the 1oo4-architecture for Safety-related systems Conforming to IEC61508

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Journal of Physics: Conference Series 2012年第1期364卷

作者： A Hayek M Al Bokhaiti M H Schwarz J Boercsoek To whom any correspondence should be addressed Institute of Computer Architecture and System Programming University of Kassel Wilhelmshoeher Allee 71 34121 Kassel Germany

With the publication and enforcement of the standard IEC 61508 of safety related systems, recent system architectures have been presented and evaluated. Among a number of techniques and measures to the evaluation of safety integrity level (SIL) for safety-related systems, several measures such as reliability block diagrams and Markov models are used to analyze the probability of failure on demand (PFD) and mean time to failure (MTTF) which conform to IEC 61508. The current paper deals with the quantitative analysis of the novel 1oo4-architecture (one out of four) presented in recent work. Therefore sophisticated calculations for the required parameters are introduced. The provided 1oo4-architecture represents an advanced safety architecture based on on-chip redundancy, which is 3-failure safe. This means that at least one of the four channels have to work correctly in order to trigger the safety function.

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A TLM-based approach to functional verification of hardware components at different abstraction levels

A TLM-based approach to functional verification of hardware ...

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Latin American Test Workshop, LATW

作者： Mikhail Chupilko Alexander Kamkin Institute for System Programming RAS Moscow Russia

Verification has long been recognized as an integral part of the hardware design process. When designing a system, engineers usually use various design representations and concretize them step by step up to a physical layout. At the beginning of the process, when there is much of indeterminacy, only abstract reference models are applicable to verification; when the process is close to the end, more concrete ones can be utilized. The article concerns problems of developing reusable verification systems (testbenches), which can be used to analyze different versions of the same component at different abstraction levels. We suggest an approach to construct reusable reaction checkers basing on a concept of Transaction Level Modeling (TLM). The paper includes general description of the approach, considers several particular cases, and outlines our experience.

关键词： Adaptation models Computational modeling Hardware Generators Computer architecture Detectors Time domain analysis

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Towards safe data flow processing by integration of design by contract in deterministic UML activities

Towards safe data flow processing by integration of design b...

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2011 23rd International Symposium on Information, Communication and Automation Technologies, ICAT 2011

作者： Daw, Zamira Vetter, Marcus Boercsoek, Josef Institute of Embedded Systems Hochschule Mannheim - University of Applied Sciences Mannheim Germany Dept. of Computer Architecture and System Programming University of Kassel Kassel Germany

ISBN: (纸本)9781457707469

Data flow processing is a common task of embedded systems which is usually modeled as a pipeline. Errors in a block of this pipeline can be propagated through it thus leading to unexpected and erroneous behaviors. For safety related applications, this pipeline has to be able to identify and react to failures. The DMOSES model-driven development method uses deterministic UML activities to describe and implement data flow processing. This method ensures deterministic behavior of concurrent processing. Design by Contract defines formal, precise and verifiable interfaces for software components. We propose a development method for safe data flow processing based on the integration of this concept in deterministic UML activities. This integration allows the identification of errors by detection of contracts violation. This paper presents an extension of the DMOSES tool for contracts verification at the model level and their monitoring at runtime. © 2011 IEEE.

关键词： Pipelines

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Simulation-based hardware verification with time-abstract models

Simulation-based hardware verification with time-abstract mo...

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East-West Design & Test Symposium (EWDTS)

作者： Alexander Kamkin Institute for System Programming Russian Academy of Science Moscow Russia

关键词： Adaptation models Hardware Delay Data models Data communication Encyclopedias Synchronization

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Automatic Backward Compatibility Analysis of Software Component Binary Interfaces

Automatic Backward Compatibility Analysis of Software Compon...

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2011 IEEE International Conference on Computer Science and Automation Engineering(CSAE 2011)

作者： Andrey Ponomarenko Vladimir Rubanov Institute for System Programming of the Russian Academy of Sciences (ISPRAS) Moscow Russia

This paper discusses a problem of ensuring backward compatibility when developing software components (e.g., libraries) and their consistent combinations (software platforms). Linux environment is considered as the main example. Breakage of the compatibility may result in crashing or incorrect behavior (at binary level) or inability to build (at source level) of applications targeted at an old version of a dependent software component when the applications are used with a new version of the component. The paper describes typical issues that cause compatibility problems (focusing on binary level problems) and presents a new method for automated verification for such issues (focusing on changes in structure of interfaces) for components developed in C/C++. Existing means can detect only a small fraction of all possible backward compatibility problems while the suggested method can verify a broad spectrum of them. The method is based on comparison of function signatures and type definitions obtained from library header files in addition to analyzing symbols in library binaries. This paper also describes an automated verification tool that implements the suggested method and presents some results of its practical usage.

关键词： Software component interfaces, shared libraries backward compatibility ABI Linux

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Runtime Verification of Linux Kernel Modules Based on Call Interception

Runtime Verification of Linux Kernel Modules Based on Call I...

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International Conference on Software Testing, Verification, and Validation, ICST

作者： Vladimir V. Rubanov Eugene A. Shatokhin Department of Software Engineering Institute of System Programming of the Russian Academy of Sciences Moscow Russia

Verification of Linux kernel modules and especially device drivers is a critically important task. However, due to the special nature of the kernel operation, it is very challenging to perform runtime analysis of particular kernel modules of interest without adverse influence on the rest of the kernel. Methods and tools for addressing this challenge are the main subject of this paper. The basic method for low-influence runtime analysis of interacting software modules is call interception. Shadow state techniques represent another method. In this paper, we discuss these methods including three different approaches to implement call interception. Conclusions are made about the most suitable ways for runtime analysis of kernel modules. Finally, we present KEDR framework, an extensible runtime analysis system for Linux kernel modules, which deploys these approaches to perform different types of analysis. The system can be used by the developers of kernel modules and, in particular, may be useful for building automated driver verification systems.

关键词： Kernel Driver circuits Instruments Linux Runtime Binary codes Resource management

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Integrating AADL-Based Tool Chain into Existing Industrial Processes

Integrating AADL-Based Tool Chain into Existing Industrial P...

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IEEE International Conference on Engineering of Complex Computer systems

作者： Alexey Khoroshilov Igor Koverninskiy Alexander Petrenko Alexander Ugnenko Institute for System Programming Russian Academy of Science Moscow Russia GosNIIAS Moscow Russia

The paper presents a case study of building solution for automation of Integrated Modular Avionics system design and system integration processes within existing industrial environment on base of model driven approaches. Features of modern architecture description language are discussed and experience of building a tool chain on top of one of them is described.

关键词： Unified modeling language Aerospace electronics Analytical models Computer architecture Schedules system analysis and design Architecture

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Reconfigurable Model-Based Test Program Generator for Microprocessors

Reconfigurable Model-Based Test Program Generator for Microp...

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IEEE International Conference on Software Testing Verification and Validation Workshop, ICSTW

作者： Alexander Kamkin Eugene Kornykhin Dmitry Vorobyev Software Engineering Department Institute for System Programming Russian Academy of Sciences Moscow Russia

Automatic generation and simulation of test programs is known to be the main means for verifying microprocessors. The problem is that test program generators for new designs are often developed from scratch with little reuse of well-tried components. State-of-the-art tools, like Genesys-Pro and RAVEN, meet the challenge by using a model-based approach, where a microprocessor model is separated from a platform-independent generation core. However, there is still a problem. Developing a microprocessor model is rather difficult and usually requires deep knowledge of the inner-core structure and interfaces. In this paper, we describe a concept of a reconfigurable test program generator being customized with the help of architecture specifications and configuration files, which describe parameters of the microprocessor subsystems (pipeline, memory, and others). The suggested approach eases the model development and makes it possible to apply the model-based testing in the early design stages when the microprocessor architecture is frequently modified.

关键词： Microprocessors Generators Automatic programming Microarchitecture Registers Pipelines Computer architecture

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Towards safe data flow processing by integration of design by contract in deterministic UML activities

Towards safe data flow processing by integration of design b...

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XXII International Symposium on Information, Communication and Automation Technologies, ICAT

作者： Zamira Daw Marcus Vetter Josef Boercsoek Institute of Embedded Systems Hochschule Mannheim-University of Applied Sciences Mannheim Germany Department of Computer Architecture and System Programming University of Kassel Kassel Germany

关键词： Unified modeling language Contracts Monitoring Embedded systems Object oriented modeling Safety Pins

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