A fundamental phase in the electrical systems planning is the temporal and spatial load forecasting. By changes in the structures of electricity markets and implementing policies for energy optimization, it is necessa...
详细信息
The advance of image processing makes knowledge-based automatic image interpretation much more realistic than ever. In the domain of remote sensing image processing, the introduction of knowledge enhances the confiden...
详细信息
We are developing a measurement device by means of which gait information can be obtained that cannot be obtained by existent devices. We are also evaluating the effectiveness of the device in rehabilitation programs....
详细信息
This paper explores a method for creating large-scale urban 3D models from GIS spatial data. It is capable of automatic generation of realistic VR models based on existing GIS data. Parametric 3D models of houses are ...
详细信息
Reputation systems are very useful in large online communities in which users may frequently have the opportunity to interact with users with whom they have no prior experience. Recently, how to enhance the cooperativ...
详细信息
Sub-threshold design of CMOS logic circuits is important for ultra low-power operation. With continuous scaling of MOS devices to nanometer sizes however, conventional CMOS logic style may not function properly at 65 ...
详细信息
Sub-threshold design of CMOS logic circuits is important for ultra low-power operation. With continuous scaling of MOS devices to nanometer sizes however, conventional CMOS logic style may not function properly at 65 nm and below due to a variety of leakage currents flowing. Thus alternative logic styles, such as, transmission-gate, have been proposed for sub-threshold operation in nanometer regime. In this work, a new CMOS logic style, that results in reduced leakage currents both in active and idle modes of operation leading to a better static and dynamic performance, is proposed. Simulations have been carried out in Cadence Spectre to verify the functionality of the gates using standard 65 nm technology. Results indicate that static power reduction of up to 25% has been achieved. The utility of the new logic style is demonstrated with a 1-bit full-adder circuit.
In multicore environment, using multiple threads is a common useful approach to improve application performance. Nevertheless, even in many simple applications, the performance might degrade when the number of threads...
详细信息
ISBN:
(纸本)9781424449316
In multicore environment, using multiple threads is a common useful approach to improve application performance. Nevertheless, even in many simple applications, the performance might degrade when the number of threads increases. Users usually impute this phenomenon to the overhead of creation or termination of threads. However, in our observation, the more significant effect is the dispatching of threads. We discuss the problems on using threads, and present a novel user dispatching mechanism (UDispatch) that provides controllability in user space to improve application performance. Since user threads cannot directly control system resources, a virtual device is adopted between user space and operating system for portability and efficiency instead of adding new system calls through kernel modification. We also experiment UDispatch through multithreading multimedia applications. The results show that a skipline application speeds up to 111.3% and 111.6% on a 4-core machine and an 8-core machine, respectively, and an optimized H.264/AVC decoder speeds up to 18.4% on a 4-core machine.
Decimal data processing applications have grown exponentially in recent years thereby increasing the need to have hardware support for decimal arithmetic. In this paper, an improved architecture for efficient Binary C...
详细信息
ISBN:
(纸本)9781424444083
Decimal data processing applications have grown exponentially in recent years thereby increasing the need to have hardware support for decimal arithmetic. In this paper, an improved architecture for efficient Binary Coded Decimal (BCD) addition/subtraction is presented that performs binary addition/subtraction without any extra hardware. The architecture works for both signed and unsigned numbers. The design is runtime reconfigurable and maximum utilization of the hardware is a feature of the architecture. Simulation results show that the proposed architecture is at least 32% better in terms of power-delay product than the existing designs.
An objective of this paper is to present experiences with teaching of an abstract computational model Random Access Machine (RAM) as a part of the theoretical computer science course. A possibility of using simulation...
详细信息
IEEE 802.16, popularly known as WiMAX, is one of the most innovative methods developed in recent times to address growing demand for high-speed wireless broadband networks. This paper addresses the problems concerning...
详细信息
IEEE 802.16, popularly known as WiMAX, is one of the most innovative methods developed in recent times to address growing demand for high-speed wireless broadband networks. This paper addresses the problems concerning the delivery of video packets in video conferencing and other multimedia application services over WiMAX. Multiple competing traffic sources over a point-to-multipoint WiMAX topology is modeled. The performance analysis on the capacity of the WiMAX equipment to handle VoIP and video traffic flows was conducted. Parameters that indicate quality of service, such as, throughput, packet loss, average jitter and average delay, are analyzed for different types of service flows as defined in WiMAX.
暂无评论