This paper considers nonlinear dynamical networks consisting of individually iISS (integral input-to-state stable) subsystems which are not necessarily ISS (input-to-state stable). Stability criteria for internal and ...
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ISBN:
(纸本)9781467320658
This paper considers nonlinear dynamical networks consisting of individually iISS (integral input-to-state stable) subsystems which are not necessarily ISS (input-to-state stable). Stability criteria for internal and external stability of the networks are developed in view of both necessity and sufficiency. For the sufficiency, we show how we can construct a Lyapunov function of the network explicitly under the assumption that a cyclic small-gain condition is satisfied. The cyclic small-gain condition is shown to be equivalent to a matrix-like condition. The two conditions and their equivalence precisely generalize some central ISS results in the literature. Moreover, the necessity of the matrix-like condition is established. The allowable number of non-ISS subsystems for stability of the network is discussed through several necessity conditions.
Instruction-level redundancy is an effective scheme to reduce the susceptibility of microprocessors to soft errors, offering high error detection and recovery capability;however, it usually incurs significant performa...
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ISBN:
(纸本)9781467344975
Instruction-level redundancy is an effective scheme to reduce the susceptibility of microprocessors to soft errors, offering high error detection and recovery capability;however, it usually incurs significant performance degradation due to resource racing. Motivated by the fact that narrow-width operands are commonly seen in applications, we exploit data-level parallelism to accelerate instruction-level redundancy. For the instructions within sphere of replication (SoR) of data-level redundancy, normal and redundant versions of the narrow-width operand of the instruction are folded into one register to share the same functional unit during execution hence alleviating resource racing. The other instructions are all protected by instructionlevel redundancy. We run SPECint2000 benchmarks on a modified version of SimpleScalar simulator, and synthesize the extra hardware to evaluate area overhead of the proposed pipeline. Experimental results show that our acceleration scheme outperforms conventional instruction-level redundancy by 13% in IPC. Besides, the extra area overhead is negligible.
Based on the determination of a minimum dwell time, this article addresses the problem of characterising a switching strategy for ℋ∞ stabilisation of switched linear stochastic systems with adapted external inputs. S...
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Based on the determination of a minimum dwell time, this article addresses the problem of characterising a switching strategy for ℋ∞ stabilisation of switched linear stochastic systems with adapted external inputs. Sufficient conditions that assure exponential mean square stability and an ℋ∞ performance index are established by analysing the time evolution of the second-order moment of the state and a recursive dynamic programming inequality, respectively. Alternative conditions are derived for numerical implementations. The proposed method is illustrated by numerical simulations. [ABSTRACT FROM AUTHOR]
Cloud computing is a new computing model. The resource monitoring tools are immature compared to traditional distributed computing and grid computing. In order to better monitor the virtual resource in cloud computing...
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Cloud computing is a new computing model. The resource monitoring tools are immature compared to traditional distributed computing and grid computing. In order to better monitor the virtual resource in cloud computing, a periodically and event-driven push (PEP) monitoring model is proposed. Taking advantage of the push and event-driven mechanism, the model can provide comparatively adequate information about usage and status of the resources. It can simplify the communication between Master and Work Nodes without missing the important issues happened during the push interval. Besides, we develop "mon" to make up for the deficiency of Libvirt in monitoring of virtual CPU and memory.
The challenge for on-chip networks is to provide low latency communication in a very low power budget. To reduce the latency and keep the simplicity of a mesh network, torus network is proposed. As torus networks have...
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If the route computation operation in an adaptive router returns more than one output channels, the selection strategy chooses one from them based on the congestion metric used. The effectiveness of a selection strate...
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Data flow processing is a common task of embedded systems which is usually modeled as a pipeline. Errors in a block of this pipeline can be propagated through it thus leading to unexpected and erroneous behaviors. For...
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Future surveillance systems will be highly heterogeneous systems consisting of Smart Cameras mixed with many other types of Smart Sensors. Although the ongoing advances in computerarchitecture make way for performanc...
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Future surveillance systems will be highly heterogeneous systems consisting of Smart Cameras mixed with many other types of Smart Sensors. Although the ongoing advances in computerarchitecture make way for performance improvements even in the smallest sensor nodes, their processing and communication capabilities will still differ from the computation power of Smart Cameras. Moreover, energy consumption is still a major concern of sensor networks. Even with highly developed batteries, reducing the energy consumption wherever possible remains a major task of system architects. Thus, it is an important design criteria for storage control algorithms. This work proposes an adaptive management system which optimizes the storage behaviour of heterogeneous sensor systems while preserving easiest accessibility of the data by the user.
Video streams are increasing by the development of network environments and price reduction of camera devices. Therefore needs of applications for querying video streams such as surveillance systems are on the increas...
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A critical concern for post-silicon debug is the need to control the chip at clock cycle level. In a single clock chip, run-stop control can be implemented by gating the clock signal using a stop signal. However, data...
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