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IEEE Symposium on Bioinformatics and Bioengineering (BIBE)

作者： Yi-Ming Sun Wei-Li Liao Hsien-Da Huang Baw-Jhiune Liu Cheng-Wei Chang Jorng-Tzong Horng Li-Ching Wu Department of Computer Science and Information Engineering National Central University Jhongli Taiwan Department of Computer Science and Information Engineering Yuan-Ze University Jhongli Taiwan Department of Information Management Hsing Wu College Taipei Taiwan Department of Biological Science & Technology Institute of Bioinformatics and Systems Biology National Chiao Tung University Hsinchu Taiwan Department of Bioinformatics Asia University Wufeng Taiwan Graduate Institute of System Biology and Bioinformatics National Central University Jhongli Taiwan

During gene expression, transcription factors are unable to bind to a transcription binding site (TFBS) involved in regulation if DNA methylation has occurred at the TFBS. Methyl-CpG-binding proteins may also occupy the TFBS and prevent the functioning of a transcription factor. Thus, the methylation status of CpG sites is an important issue when trying to understand gene regulation and shows strong correlation with the TFBS involved. In addition, CpG islands would seem to undergo cell-specific and tissue-specific methylation. Such differential methylation is presented at numerous genetic loci that are essential for development. Current DNA methylation site prediction tools need to be improved so that they include TFBS features and have greater accuracy in terms of the DNA region that is involved in methylation. We developed models that compare the differences across these regions and tissues. The TFBSs, DNA properties and DNA distribution were used as features for this classification. From the results, we found some TFBSs that were able to discriminate whether a sequence was methylated or not. The sensitivity, specificity and accuracy estimated using 10-fold cross validation were 90.8%, 80.54%, and 86.07%, respectively. Thus, for these four regions and twelve tissues, the performance levels (ACC) were all greater than 80%. We propose that the differential features or methylations vary between the different regions because the features common to each DNA region made up only 50% of the top 70 features. An online predictor based on EpiMeP is available at http://140.115.51.41/EpiMeP/. Supplementary file is available at http://140.115.51.41/EpiMeP/***.

关键词： Humans DNA Support vector machines Bioinformatics Proteins computer science Predictive models systems biology Gene expression Genetics

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A Self-Repairable Microprocessor

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ECS Transactions 2009年第1期18卷

作者： Yuanjiang Xie Xiang Fu Zijian He Yang Zhao Yu Hu Xiaowei Li Institute of Computing Technology Chinese Academy of Sciences Department of Computer Science and Engineering University of California Riverside Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences No. 6 Ke-Xue-Yuan South Road Beijing Beijing 100190 China

With increasing defect density, microprocessors, especially the embedded caches, will encounter more faults. Adding spare resources to replace defective components is a widely accepted method for yield enhancement. In this work, a repair method using content addressable memory combined with spare bits, as well as a novel fault injection method is proposed. With the proposed fault injection technique, various numbers and types of faults can be flexibly injected into the silicon. A wireless sensor network system using our self-repairable microprocessor (SRP) is developed to prove the effectiveness of the proposed technique.

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DMCtrac: Distributed multi camera tracking

DMCtrac: Distributed multi camera tracking

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ACM/IEEE International Conference on Distributed Smart Cameras, ICDSC

作者： Martin Hoffmann Michael Wittke Yvonne Bernard Ramin Soleymani Jorg Hahner Institute of Systems Engineering System and Computer Architecture Leibniz Universität Hannover Hanover Germany

Advances in the field of computer vision enable smart cameras to cooperatively analyse scenes without human intervention. Large networks of autonomous, self-organising PTZ (pan, tilt, zoom) cameras require algorithms and protocols that make way for cooperation between multiple smart cameras (SCs). This paper introduces a distributed algorithm for object tracking with multiple SCs (DMCtrac). The focus lies on PTZ management issues arising in large SC systems rather than on computer vision algorithms. DMCtrac enables SCs to observe objects throughout an area under surveillance by using their PTZ abilities to follow these objects. The algorithm has been evaluated by simulation of SC systems with up to 50 SCs as used for example for people tracking and traffic analysis. Results show, that DMCtrac is able to cope with large numbers of SCs and objects and is robust towards real world disturbances like communication failure.

关键词： Cameras Search problems Tracking Surveillance Robustness Algorithm design and analysis Switches

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MIDSCA: Towards a Smart Camera architecture of mobile internet devices

MIDSCA: Towards a Smart Camera architecture of mobile intern...

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ACM/IEEE International Conference on Distributed Smart Cameras, ICDSC

作者： Michael Wittke Martin Hoffmann Jorg Hahner Christian Muller-Schloer Institute of Systems Engineering System and Computer Architecture Leibniz Universität Hannover Hanover Germany

Each mobile phone with a built-in CMOS sensor can inherently be seen as smart camera itself. Previous work in the research field of smart camera networks intensively focused on custom hardware solutions to optimise the execution of computationally intensive computer vision algorithms. In contrast, we propose an architecture for smart camera networks consisting of low-cost mobile Internet devices (e.g. mobile phones or PDAs). Due to mass production their price decreases steadily, although their processing capacity as well as their networking abilities increases. New standards like LTE promise bandwidth increases as high as 100 Mbps on the downlink, and up to 50 Mbps on the uplink. In this paper, we present MIDSCA, an architecture for self-organising smart camera networks consisting of mobile Internet devices. One component of our architecture uses visual events themselves to implement an algorithm which is able to synchronise mobile devices with the same field of view with the accuracy of one frame. This synchronisation makes way for future mobile surveillance scenarios as multiple cameras are able to establish a common notion of concurrent events. An initial prototype of MIDSCA has been developed and bases upon a Linux operating system. Evaluations show that our algorithm is highly suitable for mobile devices as it is mostly invariant with respect to distinct perspectives and illuminations.

关键词： Cameras Mobile handsets Mobile communication computer architecture computer vision Optical distortion Image motion analysis

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Creativity and HCI: From Experience to Design in Education Selected Contributions from HCIEd 2007, March 29-30, 2007, Aveiro, Portugal

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2008年

作者： Paula Kotz William Wong Joaquim Jorge Alan Dix Paula Alexandra Silva

ISBN: (纸本)9780387890210

This book constitutes the refereed proceedings ofHCIEd 2007held in Aveiro, Portugal on March 29-30, 2007. The IFIP series publishes state-of-the-art results in the sciences and technologies of information and communication. The scope of the series includes: foundations of computer science; software theory and practice; education; computer applications in technology; communication systems; systems modeling and optimization; information systems; computers and society; computer systems technology; security and protection in information processing systems; artificial intelligence; and human-computer interaction. Proceedings and post-proceedings of refereed international conferences in computer science and interdisciplinary fields are featured. These results often precede journal publication and represent the most current research. The principal aim of the IFIP series is to encourage education and the dissemination and exchange of information about all aspects of computing.

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Artificial neural networks applied to reliability and well-being assessment of composite power systems

Artificial neural networks applied to reliability and well-b...

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10th International Conference on Probabilistic Methods Applied to Power systems, PMAPS 2008

作者： Da Silva, Armando M. Leite De Resende, Leonidas C. Luiz A., Da Fonseca Manso Miranda, V. Institute of Electric System and Energy Federal University of Itajub-UNIFEI Brazil Electrical Eng. Department Federal University of Säo Joäo del-Rei-UFSJ Brazil Institute for Systems and Computer Engineering of Porto-INESC Porto Faculty of Engineering of the University of Porto-FEUP Portugal

ISBN: (纸本)9781934325216

This paper presents a new methodology for assessing both reliability and well-being indices for composite generation and transmission systems. Firstly, a transmission network reduction is applied to find an equivalent for assessing composite reliability for practical large power systems. After that, in order to classify the operating states, Artificial Neural Networks (ANNs) based on Group Method Data Handling (GMDH) techniques are used to capture the patterns of the operating states, during the beginning of the non-sequential Monte Carlo simulation (MCS). The idea is to provide the simulation process with an intelligent memory, based only on polynomial parameters, to speed up the evaluation of the operating states. For the conventional reliability assessment, the ANNs are used to classify the operating states into success and failure. However, for the well-being analysis, only success states are classified into healthy and marginal by the ANNs. The proposed methodology is applied to the IEEE Reliability Test system 1996 and to a configuration of the Brazilian South-Southeastern system.

关键词： Neural networks

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On reducing both shift and capture power for sean-based testing

On reducing both shift and capture power for sean-based test...

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2008 Asia and South Pacific Design Automation Conference, ASP-DAC

作者： Li, Jia Xu, Qiang Hu, Yu Li, Xiaowei Key Laboratory of Computer System and Architecture ICT Chinese Academy of Sciences Beijing 100080 China Graduate University Chinese Academy of Sciences Beijing 100080 China Dept. of Computer Science and Engineering Chinese University of Hong Kong Hong Kong Center for Intelligent System and Biomimetics Institute of Advanced Integration Technology CAS/CUHK Shenzhen 518067 China

ISBN: (纸本)9781424419227

Power consumption in scan-based testing is a major concern nowadays. In this paper, we present a new X-filling technique to reduce both shift power and capture power during scan tests, namely LSC-filling. The basic idea is to use as few as possible X-bits to keep the capture power under the peak power limit of the circuit under test (CUT), while using the remaining X-bits to reduce the shift power to cut down the CUT's average power consumption during scan tests as much as possible. In addition, by carefully selecting the X-filling order, our X-filling technique is able to achieve lower capture power when compared to existing methods. Experimental results on ISCAS'89 benchmark circuits show the effectiveness of the proposed methodology. ©2008 IEEE.

关键词： Filling

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Improving data availability for a cluster file system through replication

Improving data availability for a cluster file system throug...

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International Symposium on Parallel and Distributed Processing (IPDPS)

作者： Jin Xiong Jianyu Li Rongfeng Tang Yiming Hu Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences China Department of Electrical & Computer Engineering and Computer Science University of Cincinnati USA

Data availability is a challenging issue for large- scale cluster file systems built upon thousands of individual storage devices. Replication is a well-known solution used to improve data availability. However, how to efficiently guarantee replicas consistency under concurrent conflict mutations remains a challenge. Moreover, how to quickly recover replica consistency from a storage server crash or storage device failure is also a tough problem. In this paper, we present a replication-based data availability mechanism designed for a large-scale cluster file system prototype named LionFS. Unlike other replicated storage systems that serialize replica updates, LionFS introduces a relaxed consistency model to enable concurrent updating all replicas for a mutation operation, greatly reducing the latency of operations. LionFS ensures replica consistency if applications use file locks to synchronize the concurrent conflict mutations. Another novelty of this mechanism is its light-weight log, which only records failed mutations and imposes no overhead on failure-free execution and low overhead when some storage devices are unavailable. Furthermore, recovery of replica consistency needs not stop the file system services and running applications. Performance evaluation shows that our solution achieves 50-70% higher write performance than serial replica updates. The logging overhead is shown to be low, and the recovery time is proportional to the amount of data written during the failure.

关键词： File systems Genetic mutations computer crashes Large-scale systems Availability Peer to peer computing Delay Bandwidth Laboratories computer architecture

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MemoryIO: An Extended I/O Technology in Embedded systems

MemoryIO: An Extended I/O Technology in Embedded Systems

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International Conference on Networking, architecture, and Storage (NAS)

作者： Xiaojun Yang Tao Liu Fei Chen Hailiang Cheng National Research Center for Intelligent Computing Systems Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences China Graduate University of Advanced Studies (SOKENDAI) Beijing China Key Laboratory of Computer System and Architecture Institute of Computing TechnologyNational Research Center for Intelligent Computing Systems Chinese Academy and Sciences China

MemoryIO, a sort of extended I/O in embedded systems, is presented in this paper. MemoryIO makes it powerful for embedded systems to achieve the high-performance interconnect. In view of the facts that the main memory system is absolutely necessary in any embedded system, and not all embedded systems integrate HyperTransport (HT), PCI Express or RapidIO interface, the MemoryIO based interconnect in embedded systems has more universalities compared with that based on HT, PCI Express or RapidIO. MemoryIO can not only thoroughly compensates for the lack of high performance data transfer channel, but also efficiently utilizes the memory bus bandwidth and the direct memory access (DMA) engine to reduce the latency for data transfer in embedded systems. This paper discusses some key technologies of MemoryIO, and presents its application in DCNet and the implementation of MemoryIO IP core. The MemoryIO technology can be used in various systems, but not limited to embedded systems.

关键词： Embedded system Payloads Switches Clocks Storage area networks Physical layer Protocols

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Instruction level test for parallel multipliers

Instruction level test for parallel multipliers

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15th IEEE International Conference on Electronics, Circuits and systems, ICECS 2008

作者： Lin, Ma. Yan, Gao Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences P.O. Box 2704-25 Beijing 100190 China College of Electronics and Information Engineering Tongji University SiPing Road 1239 Shanghai 200092 China Graduate University of Chinese Academy of Science Beijing 100049 China

ISBN: (纸本)9781424421824

Multiplication operations are the normal operations in operating systems or scientific calculations. Multipliers embedded in processors, DSP or SoC are well optimized for best performance, and they are sensitive to test overhead. Instruction level test is a popular functional test approach for microprocessors test, and it can get satisfactory test results. But for the multipliers, one important part of microprocessors, there is no detail on how to testing them. This paper presents an instruction level test approach for the multiplier test. The proposed approach does not modify the multipliers and does not need any extra logic just using instructions of the processors to test processors' multipliers. Sequentially it does not have any test cost on area or timing. Moreover the instruction-level test is suited for at-speed test in nature. Experimental results on the real processor's circuits show that the instruction level test approach has good effect on parallel multipliers © 2008 IEEE.

关键词： system-on-chip

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